Packaging Databook, Ch. 11: international packing specifications with rules and standards.
Chapter 11 International Packaging Specifications: A listing of international packaging specifications and a comprehensive resource library.
Packaging Databook, Ch. 14: ball grid array packaging with electrical modeling, performance, and physical structure.
Chapter 14 Ball Grid Array (BGA) Packaging: A profile of the Intel Ball Grid Array technology detailing its physical structure, electrical modeling, performance, and other aspects of the BGA packaging.
Human Interface Infrastructure Specification describes how the Intel® Platform Innovation Framework for EFI manages user input.
Describes how the Intel® Platform Innovation Framework for EFI manages user input for string and font management, driver execution environment, boot device selection, and internal and external representations.
Defines core code for an implementation of the Pre-EFI Initialization phase of the Intel® Platform Innovation Framework for EFI.
This specification defines the core code and services that are required for an implementation of the Pre-EFI Initialization (PEI) phase of the Intel® Platform Innovation Framework for EFI.
Validation results for DDR3 RDIMMS on Intel® Itanium® processor 9300-based motherboards.
Test results of a small sample of DDR3 RDIMMs on Intel® Itanium® processor-based motherboards. Use this information as a guide to module compatibility with Intel® server reference platforms using the Intel® Itanium® processors 9300 series.
White Paper: Itanium® processors are optimized for Explicitly Parallel Instruction Computing, enhancing parallelism for superior performance.
White Paper: The Intel® Itanium® processor 9500 series is optimized for Explicitly Parallel Instruction Computing principles, which exploit parallelism on all levels—pipeline, core, thread, memory, and instructions—to deliver superior performance.