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Intel® Setup and Configuration Software (Intel® SCS)

Intel® vPro™ technology features find, setup, configure, and maintain secure connections to managed devices on your network.

Intel® 22nm Technology

Introducing 3-D transistors manufactured at 22nm for future microprocessor families, continuing pursuit of Moore's Law.

Intel’s Tick Tock Model

Intel's Tick-Tock model maintains an innovation cadence in microprocessor manufacturing and microarchitecture with new advancements every other year.

Intel® 32nm Logic and SOC Technologies

The innovative Intel 32nm logic technology is a revolutionary technical breakthrough, which delivers record NMOS and PMOS transistor performance.

Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K

Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K, an option for the 45nm high-performance logic technology node.

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Strained Germanium QWFE Transistor as P-Channel Device Option for Low Power III-V CMOS Architecture

Demonstrates a Germanium p-channel QWFET with thin scaled TOXE and high mobility, delivering four times higher hole mobility.

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Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate

Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

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High-κ Gate Dielectrics, Metal Gate Electrodes in Silicon and Non-Silicon Logic Nanotechnology

Discusses low gate-leakage silicon and non-silicon transistor nanotechnology using high-κ gate dielectrics and metal gate electrodes.

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High-k/Metal-Gate Stack and Its MOSFET Characteristics

Article, IEEE Election Device Letters, Vol 25, No. 6, June 2004: High-k/Metal-Gate Stack and Its MOSFET Characteristics.

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Non-Planar, Multi-Gate InGaAs QWFETs with High-K Gate Dielectric and Ultra Scaled Gate-to-Drain/Gate-to-Source Separation

Paper: non-planar, multi-gate InGaAs QWFETs with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations of 5nm.

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