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EFI Pre-EFI Initialization Core Interface Specification v0.91

Defines core code for an implementation of the Pre-EFI Initialization phase of the Intel® Platform Innovation Framework for EFI.

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EFI SMBus Host Controller Protocol Specification v0.9

Defines the core code, services, and design required in the SMBus Host Controller Protocol for the Intel® Platform Innovation Framework for EFI.

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EFI PCI Host Bridge Resource Allocation Protocol Spec v0.9

PCI Host Bridge Resource Allocation Protocol Specification for the Intel® Platform Innovation Framework for EFI defines core code and implementation.

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EFI SMBus PPI Specification v0.9

Defines the core code, services, and design required in the system management bus PEIM to PEIM for the Intel® Platform Innovation Framework for EFI.

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EFI System Management Mode Core Interface Spec(SMM CIS) v0.91

Defines core code for an implementation of the System Management Mode phase of the Intel® Platform Innovation Framework for EFI.

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EFI Cache Subclass Specification v0.9

Defines core code for an implementation of the cache data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI Hot-Plug PCI Initialization Protocol Specification v0.9

Hot-Plug PCI Initialization Protocol Specification for the Intel® Platform Innovation Framework for EFI defines the core code for implementation.

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EFI Capsule Specification v0.9

Describes data process passed from runtime applications to reboot phases in implementation of the Intel® Platform Innovation Framework for EFI.

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EFI Memory Subclass Specification v0.9

Specification defines required core code and services for the memory data hub subclass of the Intel® Platform Innovation Framework for EFI.

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Platform Innovation Framework: UEFI Architecture Spec v0.9

Describes the architecture of the Intel® Platform Innovation Framework for EFI.

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