Software tracing: Intel® Xeon® processors support Architectural Event Trace (AET) capability to augment debuggers by helping track the execution path by showing a trace of events that occurred during the software execution. AET is enabled by setting bits in a model-specific register (MSR), thereby instrumenting monitoring of software execution without directly modifying the software itself. This generates Intel® architecture state information (data) for architecture events as they are encountered.
Examples of architectural events are interrupts, exceptions, read from model-specific register (RDMSR), write to model-specific register (WRMSR), IN/OUT instructions, code/data breakpoints, system management interrupt (SMI), and MWAIT. State information may be obtained directly over a debug port or stored in memory, time-stamped, and further processed by debug tools to analyze software execution. During platform debug, software debuggers can also set up to trigger and stop on failing conditions.
Hardware tracing: Intel Xeon processor–based platforms support capabilities to observe key internal buses and nodes that are useful for both hardware and software developers. While software is executing on the processor, transactions and events inside the CPU can be traced in real time to aid in debug of system failures. These capabilities are provided through debug tools from Intel as well as third-party debug solution providers. While transactions traced may vary from product to product due to differences in microarchitecture, information is provided about memory, I/O traffic, events requested by software, core ID, special cycles, and cache coherency attributes, thus helping to debug common use cases such as system hangs, I/O failures and platform interaction, data corruption, power issues, and more.
Debug ports: Intel Xeon–based platforms will continue to support the debug ports supported in previous-generation Intel® Core™ processor–based products.
Intel® Silicon View Technology (Intel® SVT) supports electrical validation of CPU interfaces, including PCIe* graphics, direct media interface (DMI), and double data rate (DDR), and platform controller hub (PCH) interfaces, including SATA, USB, DMI, and PCIe, on Intel Xeon–based platforms. These capabilities span across both functional and synthetic mode testing with stressful pseudorandom pattern generation. Features include timing and voltage margin, bit error ratio (BER) tests, full eye margin, equalization, and transmitter swing control. The capabilities are complemented with powerful reporting, visualization, and analytical features such as validation methodology and eye mask guidance.
Intel SVT helps test CPU and PCH interfaces on Intel Xeon–based platforms. Test patterns are written and read, at speed, independent of an operating system running on the target. The patterns are diagnosed for defects. Test tools are available to sequence power, test clocks, and margin interfaces to increase defect coverage.
Contact your Intel representative to learn how you can get access to those technologies that require a non-disclosure agreement (NDA).