"Pin Information for the IntelŽ CycloneŽ10 10CL080 Device Version 2019.03.29 Notes (1), (2)" Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Emulated LVDS Output Channel F484 B1 VREFB1N0 IO DIFFIO_L1p G4 B1 VREFB1N0 IO DIFFIO_L1n G3 B1 VREFB1N0 IO DIFFIO_L2p B2 B1 VREFB1N0 IO DIFFIO_L2n B1 B1 VREFB1N0 IO VREFB1N0 G5 B1 VREFB1N0 IO DIFFIO_L3p E4 B1 VREFB1N0 IO DIFFIO_L3n E3 B1 VREFB1N0 IO DIFFIO_L5p D2 B1 VREFB1N0 IO "DATA1,ASDO" DIFFIO_L5n D1 B1 VREFB1N0 IO H7 B1 VREFB1N0 IO DIFFIO_L6p H6 B1 VREFB1N0 IO DIFFIO_L6n J6 B1 VREFB1N0 IO DIFFIO_L7p H4 B1 VREFB1N1 IO DIFFIO_L7n H3 B1 VREFB1N1 IO "FLASH_nCE,nCSO" DIFFIO_L8p E2 B1 VREFB1N1 IO DIFFIO_L8n E1 B1 VREFB1N1 IO DIFFIO_L9p F2 B1 VREFB1N1 IO DIFFIO_L9n F1 B1 VREFB1N1 IO J5 B1 VREFB1N1 IO VREFB1N1 H5 B1 VREFB1N1 nSTATUS nSTATUS K6 B1 VREFB1N1 IO DPCLK0 DIFFIO_L12p J4 B1 VREFB1N1 IO DIFFIO_L13p H2 B1 VREFB1N1 IO DIFFIO_L13n H1 B1 VREFB1N2 IO VREFB1N2 J3 B1 VREFB1N2 IO DIFFIO_L17p J2 B1 VREFB1N2 IO DIFFIO_L17n J1 B1 VREFB1N2 IO DCLK K2 B1 VREFB1N2 IO DATA0 K1 B1 VREFB1N2 nCONFIG nCONFIG K5 B1 VREFB1N2 TDI TDI L5 B1 VREFB1N2 TCK TCK L2 B1 VREFB1N2 TMS TMS L1 B1 VREFB1N2 TDO TDO L4 B1 VREFB1N2 nCE nCE L3 B1 VREFB1N2 CLK0 DIFFCLK_0p G2 B1 VREFB1N2 CLK1 DIFFCLK_0n G1 B2 VREFB2N0 CLK2 DIFFCLK_1p T2 B2 VREFB2N0 CLK3 DIFFCLK_1n T1 B2 VREFB2N0 IO DIFFIO_L19p L6 B2 VREFB2N0 IO DIFFIO_L19n M6 B2 VREFB2N0 IO DIFFIO_L20p M2 B2 VREFB2N0 IO DIFFIO_L20n M1 B2 VREFB2N0 IO DIFFIO_L21p M4 B2 VREFB2N0 IO DIFFIO_L21n M3 B2 VREFB2N0 IO DIFFIO_L22p N2 B2 VREFB2N0 IO DIFFIO_L22n N1 B2 VREFB2N0 IO VREFB2N0 M5 B2 VREFB2N0 IO DIFFIO_L23p P2 B2 VREFB2N0 IO DIFFIO_L23n P1 B2 VREFB2N0 IO DIFFIO_L24p R2 B2 VREFB2N0 IO DIFFIO_L24n R1 B2 VREFB2N0 IO DIFFIO_L25n N5 B2 VREFB2N1 IO DPCLK1 DIFFIO_L26p P4 B2 VREFB2N1 IO DIFFIO_L26n P3 B2 VREFB2N1 IO DIFFIO_L27p U2 B2 VREFB2N1 IO DIFFIO_L27n U1 B2 VREFB2N1 IO DIFFIO_L28p V2 B2 VREFB2N1 IO DIFFIO_L28n V1 B2 VREFB2N1 IO DIFFIO_L29p P5 B2 VREFB2N1 IO DIFFIO_L29n N6 B2 VREFB2N1 IO DIFFIO_L30p R4 B2 VREFB2N1 IO DIFFIO_L30n R3 B2 VREFB2N1 IO DIFFIO_L31p W2 B2 VREFB2N1 IO DIFFIO_L31n W1 B2 VREFB2N1 IO DIFFIO_L32p Y2 B2 VREFB2N1 IO DIFFIO_L32n Y1 B2 VREFB2N1 IO VREFB2N1 T3 B2 VREFB2N2 IO RUP1 V4 B2 VREFB2N2 IO RDN1 V3 B2 VREFB2N2 IO VREFB2N2 R5 B2 VREFB2N2 IO CDPCLK1 DIFFIO_L35p T4 B2 VREFB2N2 IO DIFFIO_L35n T5 B3 VREFB3N2 IO DIFFIO_B1n V5 B3 VREFB3N2 IO DIFFIO_B3p Y4 B3 VREFB3N2 IO DIFFIO_B3n Y3 B3 VREFB3N2 IO CDPCLK2 Y6 B3 VREFB3N2 IO PLL1_CLKOUTp AA3 B3 VREFB3N2 IO PLL1_CLKOUTn AB3 B3 VREFB3N2 IO DIFFIO_B4p W6 B3 VREFB3N2 IO AA4 B3 VREFB3N2 IO VREFB3N2 AB4 B3 VREFB3N2 IO DIFFIO_B5p AA5 B3 VREFB3N2 IO DIFFIO_B5n AA6 B3 VREFB3N2 IO DIFFIO_B6p AB6 B3 VREFB3N2 IO DIFFIO_B6n AB5 B3 VREFB3N2 IO DIFFIO_B7p W7 B3 VREFB3N2 IO DIFFIO_B7n Y7 B3 VREFB3N2 IO DIFFIO_B8p U9 B3 VREFB3N2 IO DIFFIO_B8n V8 B3 VREFB3N2 IO W8 B3 VREFB3N1 IO DIFFIO_B10p AA7 B3 VREFB3N1 IO DIFFIO_B10n AB7 B3 VREFB3N1 IO DIFFIO_B11p Y8 B3 VREFB3N1 IO VREFB3N1 V9 B3 VREFB3N1 IO DPCLK2 DIFFIO_B15p V10 B3 VREFB3N0 IO DIFFIO_B16n U10 B3 VREFB3N0 IO DIFFIO_B17p AA8 B3 VREFB3N0 IO DIFFIO_B17n AB8 B3 VREFB3N0 IO DIFFIO_B18p AA9 B3 VREFB3N0 IO DPCLK3 DIFFIO_B18n AB9 B3 VREFB3N0 IO VREFB3N0 U11 B3 VREFB3N0 IO V11 B3 VREFB3N0 IO DIFFIO_B22p W10 B3 VREFB3N0 IO DIFFIO_B22n Y10 B3 VREFB3N0 IO DIFFIO_B23p AA10 B3 VREFB3N0 IO DIFFIO_B23n AB10 B3 VREFB3N0 CLK15 DIFFCLK_6p AA11 B3 VREFB3N0 CLK14 DIFFCLK_6n AB11 B4 VREFB4N2 CLK13 DIFFCLK_7p AA12 B4 VREFB4N2 CLK12 DIFFCLK_7n AB12 B4 VREFB4N2 IO DIFFIO_B25p AA13 B4 VREFB4N2 IO DIFFIO_B25n AB13 B4 VREFB4N2 IO DIFFIO_B27p AA14 B4 VREFB4N2 IO DIFFIO_B27n AB14 B4 VREFB4N2 IO VREFB4N2 V12 B4 VREFB4N2 IO DIFFIO_B28p W13 B4 VREFB4N2 IO DPCLK4 DIFFIO_B28n Y13 B4 VREFB4N2 IO DIFFIO_B29p AA15 B4 VREFB4N2 IO DIFFIO_B29n AB15 B4 VREFB4N2 IO DIFFIO_B30p U12 B4 VREFB4N2 IO DIFFIO_B31p Y14 B4 VREFB4N2 IO DIFFIO_B31n Y15 B4 VREFB4N1 IO DIFFIO_B32p AA16 B4 VREFB4N1 IO DIFFIO_B32n AB16 B4 VREFB4N1 IO DPCLK5 DIFFIO_B33p V13 B4 VREFB4N1 IO DIFFIO_B33n W14 B4 VREFB4N1 IO DIFFIO_B35p V14 B4 VREFB4N1 IO DIFFIO_B35n U14 B4 VREFB4N1 IO DIFFIO_B36p U15 B4 VREFB4N1 IO DIFFIO_B36n V15 B4 VREFB4N1 IO DIFFIO_B37p W15 B4 VREFB4N1 IO DIFFIO_B38n T15 B4 VREFB4N1 IO AB18 B4 VREFB4N1 IO VREFB4N1 AA18 B4 VREFB4N0 IO RUP2 AA19 B4 VREFB4N0 IO RDN2 AB19 B4 VREFB4N0 IO DIFFIO_B40p W17 B4 VREFB4N0 IO CDPCLK3 DIFFIO_B40n Y17 B4 VREFB4N0 IO DIFFIO_B41p AA20 B4 VREFB4N0 IO DIFFIO_B41n AB20 B4 VREFB4N0 IO VREFB4N0 V16 B4 VREFB4N0 IO DIFFIO_B44p U16 B4 VREFB4N0 IO DIFFIO_B44n U17 B4 VREFB4N0 IO PLL4_CLKOUTp T16 B4 VREFB4N0 IO PLL4_CLKOUTn R16 B4 VREFB4N0 IO DIFFIO_B45p R14 B5 VREFB5N2 IO DIFFIO_R41n AA22 B5 VREFB5N2 IO DIFFIO_R41p AA21 B5 VREFB5N2 IO RUP3 T17 B5 VREFB5N2 IO RDN3 T18 B5 VREFB5N2 IO CDPCLK4 W20 B5 VREFB5N2 IO VREFB5N2 W19 B5 VREFB5N2 IO DIFFIO_R40n Y22 B5 VREFB5N2 IO DIFFIO_R40p Y21 B5 VREFB5N2 IO DIFFIO_R39n U20 B5 VREFB5N2 IO DIFFIO_R39p U19 B5 VREFB5N2 IO DIFFIO_R37n W22 B5 VREFB5N2 IO DIFFIO_R37p W21 B5 VREFB5N1 IO DIFFIO_R36n T20 B5 VREFB5N1 IO DIFFIO_R36p T19 B5 VREFB5N1 IO DIFFIO_R35n R17 B5 VREFB5N1 IO DIFFIO_R34n V22 B5 VREFB5N1 IO DIFFIO_R34p V21 B5 VREFB5N1 IO DIFFIO_R33n R20 B5 VREFB5N1 IO DIFFIO_R32n U22 B5 VREFB5N1 IO DIFFIO_R32p U21 B5 VREFB5N1 IO DIFFIO_R31n R18 B5 VREFB5N1 IO DIFFIO_R31p R19 B5 VREFB5N1 IO DIFFIO_R29n R22 B5 VREFB5N1 IO DIFFIO_R29p R21 B5 VREFB5N1 IO VREFB5N1 P20 B5 VREFB5N0 IO DIFFIO_R27n P22 B5 VREFB5N0 IO DIFFIO_R27p P21 B5 VREFB5N0 IO DIFFIO_R25n N20 B5 VREFB5N0 IO VREFB5N0 N19 B5 VREFB5N0 IO DPCLK6 DIFFIO_R24p N18 B5 VREFB5N0 IO DEV_OE DIFFIO_R23n N22 B5 VREFB5N0 IO DEV_CLRn DIFFIO_R23p N21 B5 VREFB5N0 IO DIFFIO_R22n M22 B5 VREFB5N0 IO DIFFIO_R22p M21 B5 VREFB5N0 IO DIFFIO_R21n M20 B5 VREFB5N0 IO DIFFIO_R21p M19 B5 VREFB5N0 IO M16 B5 VREFB5N0 CLK7 DIFFCLK_3n T22 B5 VREFB5N0 CLK6 DIFFCLK_3p T21 B6 VREFB6N2 CLK5 DIFFCLK_2n G22 B6 VREFB6N2 CLK4 DIFFCLK_2p G21 B6 VREFB6N2 CONF_DONE CONF_DONE M18 B6 VREFB6N2 MSEL0 MSEL0 M17 B6 VREFB6N2 MSEL1 MSEL1 L18 B6 VREFB6N2 MSEL2 MSEL2 L17 B6 VREFB6N2 MSEL3 MSEL3 K20 B6 VREFB6N2 IO INIT_DONE DIFFIO_R20n L22 B6 VREFB6N2 IO CRC_ERROR DIFFIO_R20p L21 B6 VREFB6N2 IO VREFB6N2 K19 B6 VREFB6N2 IO nCEO DIFFIO_R19n K22 B6 VREFB6N2 IO CLKUSR DIFFIO_R19p K21 B6 VREFB6N2 IO DPCLK7 DIFFIO_R18n J22 B6 VREFB6N2 IO DIFFIO_R18p J21 B6 VREFB6N2 IO DIFFIO_R17n H22 B6 VREFB6N2 IO DIFFIO_R17p H21 B6 VREFB6N2 IO DIFFIO_R16n K18 B6 VREFB6N2 IO DIFFIO_R16p J18 B6 VREFB6N1 IO DIFFIO_R14n F22 B6 VREFB6N1 IO DIFFIO_R14p F21 B6 VREFB6N1 IO DIFFIO_R13n J20 B6 VREFB6N1 IO DIFFIO_R13p J19 B6 VREFB6N1 IO DIFFIO_R12n H20 B6 VREFB6N1 IO DIFFIO_R12p H19 B6 VREFB6N1 IO DIFFIO_R11n E22 B6 VREFB6N1 IO DIFFIO_R11p E21 B6 VREFB6N1 IO VREFB6N1 H18 B6 VREFB6N1 IO DIFFIO_R10n D22 B6 VREFB6N1 IO DIFFIO_R10p D21 B6 VREFB6N1 IO DIFFIO_R9n F20 B6 VREFB6N1 IO DIFFIO_R9p F19 B6 VREFB6N1 IO DIFFIO_R8n G18 B6 VREFB6N1 IO DIFFIO_R8p H17 B6 VREFB6N0 IO DIFFIO_R6n C22 B6 VREFB6N0 IO DIFFIO_R6p C21 B6 VREFB6N0 IO DIFFIO_R5n B22 B6 VREFB6N0 IO DIFFIO_R5p B21 B6 VREFB6N0 IO CDPCLK5 DIFFIO_R4n C20 B6 VREFB6N0 IO VREFB6N0 D20 B6 VREFB6N0 IO DIFFIO_R1n F17 B7 VREFB7N0 IO DIFFIO_T46n E16 B7 VREFB7N0 IO DIFFIO_T46p F15 B7 VREFB7N0 IO CDPCLK6 DIFFIO_T45p F14 B7 VREFB7N0 IO DIFFIO_T44n C18 B7 VREFB7N0 IO DIFFIO_T44p D18 B7 VREFB7N0 IO VREFB7N0 D17 B7 VREFB7N0 IO DIFFIO_T42n C19 B7 VREFB7N0 IO DIFFIO_T42p D19 B7 VREFB7N0 IO PLL2_CLKOUTn A20 B7 VREFB7N0 IO PLL2_CLKOUTp B20 B7 VREFB7N0 IO DIFFIO_T40p C17 B7 VREFB7N1 IO RUP4 B19 B7 VREFB7N1 IO RDN4 A19 B7 VREFB7N1 IO DIFFIO_T39n A18 B7 VREFB7N1 IO DIFFIO_T39p B18 B7 VREFB7N1 IO DIFFIO_T38n D15 B7 VREFB7N1 IO DIFFIO_T38p E15 B7 VREFB7N1 IO DIFFIO_T36n A17 B7 VREFB7N1 IO DIFFIO_T36p B17 B7 VREFB7N1 IO DIFFIO_T35n A16 B7 VREFB7N1 IO DIFFIO_T35p B16 B7 VREFB7N1 IO VREFB7N1 C15 B7 VREFB7N1 IO DIFFIO_T33n E14 B7 VREFB7N1 IO DPCLK8 DIFFIO_T33p F13 B7 VREFB7N1 IO DIFFIO_T32n A15 B7 VREFB7N1 IO DIFFIO_T32p B15 B7 VREFB7N2 IO DIFFIO_T31n C13 B7 VREFB7N2 IO DIFFIO_T31p D13 B7 VREFB7N2 IO VREFB7N2 E13 B7 VREFB7N2 IO DIFFIO_T27n A14 B7 VREFB7N2 IO DIFFIO_T27p B14 B7 VREFB7N2 IO DIFFIO_T26n A13 B7 VREFB7N2 IO DPCLK9 DIFFIO_T26p B13 B7 VREFB7N2 IO E12 B7 VREFB7N2 IO DIFFIO_T25n E11 B7 VREFB7N2 IO DIFFIO_T25p F11 B7 VREFB7N2 CLK8 DIFFCLK_5n A12 B7 VREFB7N2 CLK9 DIFFCLK_5p B12 B8 VREFB8N0 CLK10 DIFFCLK_4n A11 B8 VREFB8N0 CLK11 DIFFCLK_4p B11 B8 VREFB8N0 IO DIFFIO_T24n D10 B8 VREFB8N0 IO DIFFIO_T23n A10 B8 VREFB8N0 IO DIFFIO_T23p B10 B8 VREFB8N0 IO DIFFIO_T22n A9 B8 VREFB8N0 IO DPCLK10 DIFFIO_T22p B9 B8 VREFB8N0 IO VREFB8N0 C10 B8 VREFB8N0 IO DATA2 DIFFIO_T19n A8 B8 VREFB8N0 IO DATA3 DIFFIO_T19p B8 B8 VREFB8N0 IO DIFFIO_T18n A7 B8 VREFB8N0 IO DATA4 DIFFIO_T18p B7 B8 VREFB8N0 IO DIFFIO_T17n A6 B8 VREFB8N0 IO DIFFIO_T17p B6 B8 VREFB8N1 IO DIFFIO_T16n E9 B8 VREFB8N1 IO DPCLK11 DIFFIO_T15n C8 B8 VREFB8N1 IO DIFFIO_T15p C7 B8 VREFB8N1 IO DIFFIO_T14n D8 B8 VREFB8N1 IO DIFFIO_T14p E8 B8 VREFB8N1 IO DATA5 DIFFIO_T13p A5 B8 VREFB8N1 IO VREFB8N1 B5 B8 VREFB8N1 IO DATA6 DIFFIO_T12p F10 B8 VREFB8N1 IO DATA7 DIFFIO_T11n C6 B8 VREFB8N1 IO DIFFIO_T11p D7 B8 VREFB8N1 IO DIFFIO_T10n A4 B8 VREFB8N1 IO DIFFIO_T10p B4 B8 VREFB8N1 IO DIFFIO_T9n F8 B8 VREFB8N1 IO DIFFIO_T7n A3 B8 VREFB8N2 IO DIFFIO_T7p B3 B8 VREFB8N2 IO VREFB8N2 D6 B8 VREFB8N2 IO DIFFIO_T6n E7 B8 VREFB8N2 IO DIFFIO_T3n C3 B8 VREFB8N2 IO CDPCLK7 DIFFIO_T3p C4 B8 VREFB8N2 IO DIFFIO_T2n F7 B8 VREFB8N2 IO DIFFIO_T2p G7 B8 VREFB8N2 IO F9 B8 VREFB8N2 IO PLL3_CLKOUTn E6 B8 VREFB8N2 IO PLL3_CLKOUTp E5 GND L10 GND L11 GND M10 GND M11 GND L12 GND L13 GND M12 GND M13 GND N11 GND K11 GND N12 GND K12 GND K13 GND N13 GND N10 GND K10 GND J9 GND F12 GND H12 GND H13 GND J15 GND K16 GND L15 GND N15 GND R13 GND R11 GND R9 GND P8 GND H14 GND H10 GND H8 GND N8 GND R7 GND T8 GND T12 GND P16 GND L8 GND G17 GND M7 GND F16 GND H16 GND G15 GND G13 GND G11 GND E10 GND G9 GND K7 GND P6 GND U7 GND V6 GND T10 GND U13 GND T14 GND N17 GND A1 GND C5 GND C9 GND C11 GND C12 GND C14 GND C16 GND A22 GND E20 GND G20 GND L20 GND P19 GND V20 GND Y20 GND AB22 GND Y18 GND Y16 GND Y12 GND Y11 GND Y9 GND Y5 GND AB1 GND N3 GND U3 GND W3 GND D3 GND F3 GND K3 GND AA2 GND AA1 GND C1 GND C2 GND AA17 GND AB17 GNDA1 U5 GNDA2 E18 GNDA3 F5 GNDA4 V18 VCCD_PLL1 U6 VCCD_PLL2 E17 VCCD_PLL3 F6 VCCD_PLL4 V17 VCCIO1 D4 VCCIO1 F4 VCCIO1 K4 VCCIO2 N4 VCCIO2 U4 VCCIO2 W4 VCCIO3 AB2 VCCIO3 W5 VCCIO3 W9 VCCIO3 W11 VCCIO4 AB21 VCCIO4 W12 VCCIO4 W16 VCCIO4 W18 VCCIO5 P18 VCCIO5 V19 VCCIO5 Y19 VCCIO6 E19 VCCIO6 G19 VCCIO6 L19 VCCIO7 A21 VCCIO7 D12 VCCIO7 D14 VCCIO7 D16 VCCIO8 A2 VCCIO8 D5 VCCIO8 D9 VCCIO8 D11 VCCA1 T6 VCCA2 F18 VCCA3 G6 VCCA4 U18 VCCINT J11 VCCINT J12 VCCINT L14 VCCINT M14 VCCINT P11 VCCINT P12 VCCINT L9 VCCINT M9 VCCINT J13 VCCINT J14 VCCINT K14 VCCINT J10 VCCINT K9 VCCINT N9 VCCINT P9 VCCINT P10 VCCINT P13 VCCINT P14 VCCINT N14 VCCINT J16 VCCINT K15 VCCINT L16 VCCINT M15 VCCINT R12 VCCINT R10 VCCINT R8 VCCINT H9 VCCINT G12 VCCINT J8 VCCINT M8 VCCINT T7 VCCINT T9 VCCINT T13 VCCINT P15 VCCINT H15 VCCINT H11 VCCINT K8 VCCINT P17 VCCINT L7 VCCINT N16 VCCINT K17 VCCINT J17 VCCINT G16 VCCINT G14 VCCINT G10 VCCINT G8 VCCINT J7 VCCINT N7 VCCINT P7 VCCINT R6 VCCINT U8 VCCINT V7 VCCINT T11 VCCINT R15 Notes: "(1) If the p pin or n pin is not available for the package, the particular differential pair is not supported." "(2) For more information about pin definition and pin connection guidelines, refer to the " Cyclone 10 LP Device Family Pin Connection Guidelines. "Pin Information for the IntelŽ CycloneŽ10 10CL080 Device Version 2019.03.29 Notes (1), (2)" Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Emulated LVDS Output Channel U484 B1 VREFB1N0 IO DIFFIO_L1p G4 B1 VREFB1N0 IO DIFFIO_L1n G3 B1 VREFB1N0 IO DIFFIO_L2p B2 B1 VREFB1N0 IO DIFFIO_L2n B1 B1 VREFB1N0 IO VREFB1N0 G5 B1 VREFB1N0 IO DIFFIO_L3p E4 B1 VREFB1N0 IO DIFFIO_L3n E3 B1 VREFB1N0 IO DIFFIO_L5p D2 B1 VREFB1N0 IO "DATA1,ASDO" DIFFIO_L5n D1 B1 VREFB1N0 IO H7 B1 VREFB1N0 IO DIFFIO_L6p H6 B1 VREFB1N0 IO DIFFIO_L6n J6 B1 VREFB1N0 IO DIFFIO_L7p H4 B1 VREFB1N1 IO DIFFIO_L7n H3 B1 VREFB1N1 IO "FLASH_nCE,nCSO" DIFFIO_L8p E2 B1 VREFB1N1 IO DIFFIO_L8n E1 B1 VREFB1N1 IO DIFFIO_L9p F2 B1 VREFB1N1 IO DIFFIO_L9n F1 B1 VREFB1N1 IO J5 B1 VREFB1N1 IO VREFB1N1 H5 B1 VREFB1N1 nSTATUS nSTATUS K6 B1 VREFB1N1 IO DPCLK0 DIFFIO_L12p J4 B1 VREFB1N1 IO DIFFIO_L13p H2 B1 VREFB1N1 IO DIFFIO_L13n H1 B1 VREFB1N2 IO VREFB1N2 J3 B1 VREFB1N2 IO DIFFIO_L17p J2 B1 VREFB1N2 IO DIFFIO_L17n J1 B1 VREFB1N2 IO DCLK K2 B1 VREFB1N2 IO DATA0 K1 B1 VREFB1N2 nCONFIG nCONFIG K5 B1 VREFB1N2 TDI TDI L5 B1 VREFB1N2 TCK TCK L2 B1 VREFB1N2 TMS TMS L1 B1 VREFB1N2 TDO TDO L4 B1 VREFB1N2 nCE nCE L3 B1 VREFB1N2 CLK0 DIFFCLK_0p G2 B1 VREFB1N2 CLK1 DIFFCLK_0n G1 B2 VREFB2N0 CLK2 DIFFCLK_1p T2 B2 VREFB2N0 CLK3 DIFFCLK_1n T1 B2 VREFB2N0 IO DIFFIO_L19p L6 B2 VREFB2N0 IO DIFFIO_L19n M6 B2 VREFB2N0 IO DIFFIO_L20p M2 B2 VREFB2N0 IO DIFFIO_L20n M1 B2 VREFB2N0 IO DIFFIO_L21p M4 B2 VREFB2N0 IO DIFFIO_L21n M3 B2 VREFB2N0 IO DIFFIO_L22p N2 B2 VREFB2N0 IO DIFFIO_L22n N1 B2 VREFB2N0 IO VREFB2N0 M5 B2 VREFB2N0 IO DIFFIO_L23p P2 B2 VREFB2N0 IO DIFFIO_L23n P1 B2 VREFB2N0 IO DIFFIO_L24p R2 B2 VREFB2N0 IO DIFFIO_L24n R1 B2 VREFB2N0 IO DIFFIO_L25n N5 B2 VREFB2N1 IO DPCLK1 DIFFIO_L26p P4 B2 VREFB2N1 IO DIFFIO_L26n P3 B2 VREFB2N1 IO DIFFIO_L27p U2 B2 VREFB2N1 IO DIFFIO_L27n U1 B2 VREFB2N1 IO DIFFIO_L28p V2 B2 VREFB2N1 IO DIFFIO_L28n V1 B2 VREFB2N1 IO DIFFIO_L29p P5 B2 VREFB2N1 IO DIFFIO_L29n N6 B2 VREFB2N1 IO DIFFIO_L30p R4 B2 VREFB2N1 IO DIFFIO_L30n R3 B2 VREFB2N1 IO DIFFIO_L31p W2 B2 VREFB2N1 IO DIFFIO_L31n W1 B2 VREFB2N1 IO DIFFIO_L32p Y2 B2 VREFB2N1 IO DIFFIO_L32n Y1 B2 VREFB2N1 IO VREFB2N1 T3 B2 VREFB2N2 IO RUP1 V4 B2 VREFB2N2 IO RDN1 V3 B2 VREFB2N2 IO VREFB2N2 R5 B2 VREFB2N2 IO CDPCLK1 DIFFIO_L35p T4 B2 VREFB2N2 IO DIFFIO_L35n T5 B3 VREFB3N2 IO DIFFIO_B1n V5 B3 VREFB3N2 IO DIFFIO_B3p Y4 B3 VREFB3N2 IO DIFFIO_B3n Y3 B3 VREFB3N2 IO CDPCLK2 Y6 B3 VREFB3N2 IO PLL1_CLKOUTp AA3 B3 VREFB3N2 IO PLL1_CLKOUTn AB3 B3 VREFB3N2 IO DIFFIO_B4p W6 B3 VREFB3N2 IO AA4 B3 VREFB3N2 IO VREFB3N2 AB4 B3 VREFB3N2 IO DIFFIO_B5p AA5 B3 VREFB3N2 IO DIFFIO_B5n AA6 B3 VREFB3N2 IO DIFFIO_B6p AB6 B3 VREFB3N2 IO DIFFIO_B6n AB5 B3 VREFB3N2 IO DIFFIO_B7p W7 B3 VREFB3N2 IO DIFFIO_B7n Y7 B3 VREFB3N2 IO DIFFIO_B8p U9 B3 VREFB3N2 IO DIFFIO_B8n V8 B3 VREFB3N2 IO W8 B3 VREFB3N1 IO DIFFIO_B10p AA7 B3 VREFB3N1 IO DIFFIO_B10n AB7 B3 VREFB3N1 IO DIFFIO_B11p Y8 B3 VREFB3N1 IO VREFB3N1 V9 B3 VREFB3N1 IO DPCLK2 DIFFIO_B15p V10 B3 VREFB3N0 IO DIFFIO_B16n U10 B3 VREFB3N0 IO DIFFIO_B17p AA8 B3 VREFB3N0 IO DIFFIO_B17n AB8 B3 VREFB3N0 IO DIFFIO_B18p AA9 B3 VREFB3N0 IO DPCLK3 DIFFIO_B18n AB9 B3 VREFB3N0 IO VREFB3N0 U11 B3 VREFB3N0 IO V11 B3 VREFB3N0 IO DIFFIO_B22p W10 B3 VREFB3N0 IO DIFFIO_B22n Y10 B3 VREFB3N0 IO DIFFIO_B23p AA10 B3 VREFB3N0 IO DIFFIO_B23n AB10 B3 VREFB3N0 CLK15 DIFFCLK_6p AA11 B3 VREFB3N0 CLK14 DIFFCLK_6n AB11 B4 VREFB4N2 CLK13 DIFFCLK_7p AA12 B4 VREFB4N2 CLK12 DIFFCLK_7n AB12 B4 VREFB4N2 IO DIFFIO_B25p AA13 B4 VREFB4N2 IO DIFFIO_B25n AB13 B4 VREFB4N2 IO DIFFIO_B27p AA14 B4 VREFB4N2 IO DIFFIO_B27n AB14 B4 VREFB4N2 IO VREFB4N2 V12 B4 VREFB4N2 IO DIFFIO_B28p W13 B4 VREFB4N2 IO DPCLK4 DIFFIO_B28n Y13 B4 VREFB4N2 IO DIFFIO_B29p AA15 B4 VREFB4N2 IO DIFFIO_B29n AB15 B4 VREFB4N2 IO DIFFIO_B30p U12 B4 VREFB4N2 IO DIFFIO_B31p Y14 B4 VREFB4N2 IO DIFFIO_B31n Y15 B4 VREFB4N1 IO DIFFIO_B32p AA16 B4 VREFB4N1 IO DIFFIO_B32n AB16 B4 VREFB4N1 IO DPCLK5 DIFFIO_B33p V13 B4 VREFB4N1 IO DIFFIO_B33n W14 B4 VREFB4N1 IO DIFFIO_B35p V14 B4 VREFB4N1 IO DIFFIO_B35n U14 B4 VREFB4N1 IO DIFFIO_B36p U15 B4 VREFB4N1 IO DIFFIO_B36n V15 B4 VREFB4N1 IO DIFFIO_B37p W15 B4 VREFB4N1 IO DIFFIO_B38n T15 B4 VREFB4N1 IO AB18 B4 VREFB4N1 IO VREFB4N1 AA18 B4 VREFB4N0 IO RUP2 AA19 B4 VREFB4N0 IO RDN2 AB19 B4 VREFB4N0 IO DIFFIO_B40p W17 B4 VREFB4N0 IO CDPCLK3 DIFFIO_B40n Y17 B4 VREFB4N0 IO DIFFIO_B41p AA20 B4 VREFB4N0 IO DIFFIO_B41n AB20 B4 VREFB4N0 IO VREFB4N0 V16 B4 VREFB4N0 IO DIFFIO_B44p U16 B4 VREFB4N0 IO DIFFIO_B44n U17 B4 VREFB4N0 IO PLL4_CLKOUTp T16 B4 VREFB4N0 IO PLL4_CLKOUTn R16 B4 VREFB4N0 IO DIFFIO_B45p R14 B5 VREFB5N2 IO DIFFIO_R41n AA22 B5 VREFB5N2 IO DIFFIO_R41p AA21 B5 VREFB5N2 IO RUP3 T17 B5 VREFB5N2 IO RDN3 T18 B5 VREFB5N2 IO CDPCLK4 W20 B5 VREFB5N2 IO VREFB5N2 W19 B5 VREFB5N2 IO DIFFIO_R40n Y22 B5 VREFB5N2 IO DIFFIO_R40p Y21 B5 VREFB5N2 IO DIFFIO_R39n U20 B5 VREFB5N2 IO DIFFIO_R39p U19 B5 VREFB5N2 IO DIFFIO_R37n W22 B5 VREFB5N2 IO DIFFIO_R37p W21 B5 VREFB5N1 IO DIFFIO_R36n T20 B5 VREFB5N1 IO DIFFIO_R36p T19 B5 VREFB5N1 IO DIFFIO_R35n R17 B5 VREFB5N1 IO DIFFIO_R34n V22 B5 VREFB5N1 IO DIFFIO_R34p V21 B5 VREFB5N1 IO DIFFIO_R33n R20 B5 VREFB5N1 IO DIFFIO_R32n U22 B5 VREFB5N1 IO DIFFIO_R32p U21 B5 VREFB5N1 IO DIFFIO_R31n R18 B5 VREFB5N1 IO DIFFIO_R31p R19 B5 VREFB5N1 IO DIFFIO_R29n R22 B5 VREFB5N1 IO DIFFIO_R29p R21 B5 VREFB5N1 IO VREFB5N1 P20 B5 VREFB5N0 IO DIFFIO_R27n P22 B5 VREFB5N0 IO DIFFIO_R27p P21 B5 VREFB5N0 IO DIFFIO_R25n N20 B5 VREFB5N0 IO VREFB5N0 N19 B5 VREFB5N0 IO DPCLK6 DIFFIO_R24p N18 B5 VREFB5N0 IO DEV_OE DIFFIO_R23n N22 B5 VREFB5N0 IO DEV_CLRn DIFFIO_R23p N21 B5 VREFB5N0 IO DIFFIO_R22n M22 B5 VREFB5N0 IO DIFFIO_R22p M21 B5 VREFB5N0 IO DIFFIO_R21n M20 B5 VREFB5N0 IO DIFFIO_R21p M19 B5 VREFB5N0 IO M16 B5 VREFB5N0 CLK7 DIFFCLK_3n T22 B5 VREFB5N0 CLK6 DIFFCLK_3p T21 B6 VREFB6N2 CLK5 DIFFCLK_2n G22 B6 VREFB6N2 CLK4 DIFFCLK_2p G21 B6 VREFB6N2 CONF_DONE CONF_DONE M18 B6 VREFB6N2 MSEL0 MSEL0 M17 B6 VREFB6N2 MSEL1 MSEL1 L18 B6 VREFB6N2 MSEL2 MSEL2 L17 B6 VREFB6N2 MSEL3 MSEL3 K20 B6 VREFB6N2 IO INIT_DONE DIFFIO_R20n L22 B6 VREFB6N2 IO CRC_ERROR DIFFIO_R20p L21 B6 VREFB6N2 IO VREFB6N2 K19 B6 VREFB6N2 IO nCEO DIFFIO_R19n K22 B6 VREFB6N2 IO CLKUSR DIFFIO_R19p K21 B6 VREFB6N2 IO DPCLK7 DIFFIO_R18n J22 B6 VREFB6N2 IO DIFFIO_R18p J21 B6 VREFB6N2 IO DIFFIO_R17n H22 B6 VREFB6N2 IO DIFFIO_R17p H21 B6 VREFB6N2 IO DIFFIO_R16n K18 B6 VREFB6N2 IO DIFFIO_R16p J18 B6 VREFB6N1 IO DIFFIO_R14n F22 B6 VREFB6N1 IO DIFFIO_R14p F21 B6 VREFB6N1 IO DIFFIO_R13n J20 B6 VREFB6N1 IO DIFFIO_R13p J19 B6 VREFB6N1 IO DIFFIO_R12n H20 B6 VREFB6N1 IO DIFFIO_R12p H19 B6 VREFB6N1 IO DIFFIO_R11n E22 B6 VREFB6N1 IO DIFFIO_R11p E21 B6 VREFB6N1 IO VREFB6N1 H18 B6 VREFB6N1 IO DIFFIO_R10n D22 B6 VREFB6N1 IO DIFFIO_R10p D21 B6 VREFB6N1 IO DIFFIO_R9n F20 B6 VREFB6N1 IO DIFFIO_R9p F19 B6 VREFB6N1 IO DIFFIO_R8n G18 B6 VREFB6N1 IO DIFFIO_R8p H17 B6 VREFB6N0 IO DIFFIO_R6n C22 B6 VREFB6N0 IO DIFFIO_R6p C21 B6 VREFB6N0 IO DIFFIO_R5n B22 B6 VREFB6N0 IO DIFFIO_R5p B21 B6 VREFB6N0 IO CDPCLK5 DIFFIO_R4n C20 B6 VREFB6N0 IO VREFB6N0 D20 B6 VREFB6N0 IO DIFFIO_R1n F17 B7 VREFB7N0 IO DIFFIO_T46n E16 B7 VREFB7N0 IO DIFFIO_T46p F15 B7 VREFB7N0 IO CDPCLK6 DIFFIO_T45p F14 B7 VREFB7N0 IO DIFFIO_T44n C18 B7 VREFB7N0 IO DIFFIO_T44p D18 B7 VREFB7N0 IO VREFB7N0 D17 B7 VREFB7N0 IO DIFFIO_T42n C19 B7 VREFB7N0 IO DIFFIO_T42p D19 B7 VREFB7N0 IO PLL2_CLKOUTn A20 B7 VREFB7N0 IO PLL2_CLKOUTp B20 B7 VREFB7N0 IO DIFFIO_T40p C17 B7 VREFB7N1 IO RUP4 B19 B7 VREFB7N1 IO RDN4 A19 B7 VREFB7N1 IO DIFFIO_T39n A18 B7 VREFB7N1 IO DIFFIO_T39p B18 B7 VREFB7N1 IO DIFFIO_T38n D15 B7 VREFB7N1 IO DIFFIO_T38p E15 B7 VREFB7N1 IO DIFFIO_T36n A17 B7 VREFB7N1 IO DIFFIO_T36p B17 B7 VREFB7N1 IO DIFFIO_T35n A16 B7 VREFB7N1 IO DIFFIO_T35p B16 B7 VREFB7N1 IO VREFB7N1 C15 B7 VREFB7N1 IO DIFFIO_T33n E14 B7 VREFB7N1 IO DPCLK8 DIFFIO_T33p F13 B7 VREFB7N1 IO DIFFIO_T32n A15 B7 VREFB7N1 IO DIFFIO_T32p B15 B7 VREFB7N2 IO DIFFIO_T31n C13 B7 VREFB7N2 IO DIFFIO_T31p D13 B7 VREFB7N2 IO VREFB7N2 E13 B7 VREFB7N2 IO DIFFIO_T27n A14 B7 VREFB7N2 IO DIFFIO_T27p B14 B7 VREFB7N2 IO DIFFIO_T26n A13 B7 VREFB7N2 IO DPCLK9 DIFFIO_T26p B13 B7 VREFB7N2 IO E12 B7 VREFB7N2 IO DIFFIO_T25n E11 B7 VREFB7N2 IO DIFFIO_T25p F11 B7 VREFB7N2 CLK8 DIFFCLK_5n A12 B7 VREFB7N2 CLK9 DIFFCLK_5p B12 B8 VREFB8N0 CLK10 DIFFCLK_4n A11 B8 VREFB8N0 CLK11 DIFFCLK_4p B11 B8 VREFB8N0 IO DIFFIO_T24n D10 B8 VREFB8N0 IO DIFFIO_T23n A10 B8 VREFB8N0 IO DIFFIO_T23p B10 B8 VREFB8N0 IO DIFFIO_T22n A9 B8 VREFB8N0 IO DPCLK10 DIFFIO_T22p B9 B8 VREFB8N0 IO VREFB8N0 C10 B8 VREFB8N0 IO DATA2 DIFFIO_T19n A8 B8 VREFB8N0 IO DATA3 DIFFIO_T19p B8 B8 VREFB8N0 IO DIFFIO_T18n A7 B8 VREFB8N0 IO DATA4 DIFFIO_T18p B7 B8 VREFB8N0 IO DIFFIO_T17n A6 B8 VREFB8N0 IO DIFFIO_T17p B6 B8 VREFB8N1 IO DIFFIO_T16n E9 B8 VREFB8N1 IO DPCLK11 DIFFIO_T15n C8 B8 VREFB8N1 IO DIFFIO_T15p C7 B8 VREFB8N1 IO DIFFIO_T14n D8 B8 VREFB8N1 IO DIFFIO_T14p E8 B8 VREFB8N1 IO DATA5 DIFFIO_T13p A5 B8 VREFB8N1 IO VREFB8N1 B5 B8 VREFB8N1 IO DATA6 DIFFIO_T12p F10 B8 VREFB8N1 IO DATA7 DIFFIO_T11n C6 B8 VREFB8N1 IO DIFFIO_T11p D7 B8 VREFB8N1 IO DIFFIO_T10n A4 B8 VREFB8N1 IO DIFFIO_T10p B4 B8 VREFB8N1 IO DIFFIO_T9n F8 B8 VREFB8N1 IO DIFFIO_T7n A3 B8 VREFB8N2 IO DIFFIO_T7p B3 B8 VREFB8N2 IO VREFB8N2 D6 B8 VREFB8N2 IO DIFFIO_T6n E7 B8 VREFB8N2 IO DIFFIO_T3n C3 B8 VREFB8N2 IO CDPCLK7 DIFFIO_T3p C4 B8 VREFB8N2 IO DIFFIO_T2n F7 B8 VREFB8N2 IO DIFFIO_T2p G7 B8 VREFB8N2 IO F9 B8 VREFB8N2 IO PLL3_CLKOUTn E6 B8 VREFB8N2 IO PLL3_CLKOUTp E5 GND L10 GND L11 GND M10 GND M11 GND L12 GND L13 GND M12 GND M13 GND N11 GND K11 GND N12 GND K12 GND K13 GND N13 GND N10 GND K10 GND J9 GND F12 GND H12 GND H13 GND J15 GND K16 GND L15 GND N15 GND R13 GND R11 GND R9 GND P8 GND H14 GND H10 GND H8 GND N8 GND R7 GND T8 GND T12 GND P16 GND L8 GND G17 GND M7 GND F16 GND H16 GND G15 GND G13 GND G11 GND E10 GND G9 GND K7 GND P6 GND U7 GND V6 GND T10 GND U13 GND T14 GND N17 GND A1 GND C5 GND C9 GND C11 GND C12 GND C14 GND C16 GND A22 GND E20 GND G20 GND L20 GND P19 GND V20 GND Y20 GND AB22 GND Y18 GND Y16 GND Y12 GND Y11 GND Y9 GND Y5 GND AB1 GND N3 GND U3 GND W3 GND D3 GND F3 GND K3 GND AA2 GND AA1 GND C1 GND C2 GND AA17 GND AB17 GNDA1 U5 GNDA2 E18 GNDA3 F5 GNDA4 V18 VCCD_PLL1 U6 VCCD_PLL2 E17 VCCD_PLL3 F6 VCCD_PLL4 V17 VCCIO1 D4 VCCIO1 F4 VCCIO1 K4 VCCIO2 N4 VCCIO2 U4 VCCIO2 W4 VCCIO3 AB2 VCCIO3 W5 VCCIO3 W9 VCCIO3 W11 VCCIO4 AB21 VCCIO4 W12 VCCIO4 W16 VCCIO4 W18 VCCIO5 P18 VCCIO5 V19 VCCIO5 Y19 VCCIO6 E19 VCCIO6 G19 VCCIO6 L19 VCCIO7 A21 VCCIO7 D12 VCCIO7 D14 VCCIO7 D16 VCCIO8 A2 VCCIO8 D5 VCCIO8 D9 VCCIO8 D11 VCCA1 T6 VCCA2 F18 VCCA3 G6 VCCA4 U18 VCCINT J11 VCCINT J12 VCCINT L14 VCCINT M14 VCCINT P11 VCCINT P12 VCCINT L9 VCCINT M9 VCCINT J13 VCCINT J14 VCCINT K14 VCCINT J10 VCCINT K9 VCCINT N9 VCCINT P9 VCCINT P10 VCCINT P13 VCCINT P14 VCCINT N14 VCCINT J16 VCCINT K15 VCCINT L16 VCCINT M15 VCCINT R12 VCCINT R10 VCCINT R8 VCCINT H9 VCCINT G12 VCCINT J8 VCCINT M8 VCCINT T7 VCCINT T9 VCCINT T13 VCCINT P15 VCCINT H15 VCCINT H11 VCCINT K8 VCCINT P17 VCCINT L7 VCCINT N16 VCCINT K17 VCCINT J17 VCCINT G16 VCCINT G14 VCCINT G10 VCCINT G8 VCCINT J7 VCCINT N7 VCCINT P7 VCCINT R6 VCCINT U8 VCCINT V7 VCCINT T11 VCCINT R15 Notes: "(1) If the p pin or n pin is not available for the package, the particular differential pair is not supported." "(2) For more information about pin definition and pin connection guidelines, refer to the " Cyclone 10 LP Device Family Pin Connection Guidelines. "Pin Information for the IntelŽ CycloneŽ10 10CL080 Device Version 2019.03.29 Notes (1), (2)" Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Emulated LVDS Output Channel F780 B1 VREFB1N0 IO DIFFIO_L1p D3 B1 VREFB1N0 IO DIFFIO_L1n C2 B1 VREFB1N0 IO DIFFIO_L2p D2 B1 VREFB1N0 IO DIFFIO_L2n D1 B1 VREFB1N0 IO VREFB1N0 H7 B1 VREFB1N0 IO DIFFIO_L3p G6 B1 VREFB1N0 IO DIFFIO_L3n G5 B1 VREFB1N0 IO CDPCLK0 DIFFIO_L4p E3 B1 VREFB1N0 IO DIFFIO_L4n F3 B1 VREFB1N0 IO DIFFIO_L5p F5 B1 VREFB1N0 IO "DATA1,ASDO" DIFFIO_L5n F4 B1 VREFB1N0 IO H6 B1 VREFB1N0 IO DIFFIO_L6p G4 B1 VREFB1N0 IO DIFFIO_L6n G3 B1 VREFB1N1 IO "FLASH_nCE,nCSO" DIFFIO_L8p E2 B1 VREFB1N1 IO DIFFIO_L8n E1 B1 VREFB1N1 IO DIFFIO_L9p F2 B1 VREFB1N1 IO DIFFIO_L9n F1 B1 VREFB1N1 IO H5 B1 VREFB1N1 IO VREFB1N1 L5 B1 VREFB1N1 IO DIFFIO_L10p J4 B1 VREFB1N1 IO DIFFIO_L10n J3 B1 VREFB1N1 nSTATUS nSTATUS M6 B1 VREFB1N1 IO DIFFIO_L11p G2 B1 VREFB1N1 IO DIFFIO_L11n G1 B1 VREFB1N1 IO DPCLK0 DIFFIO_L12p K2 B1 VREFB1N1 IO DIFFIO_L12n K1 B1 VREFB1N1 IO DIFFIO_L13p K4 B1 VREFB1N1 IO DIFFIO_L13n K3 B1 VREFB1N2 IO DIFFIO_L15p M4 B1 VREFB1N2 IO DIFFIO_L15n M3 B1 VREFB1N2 IO N4 B1 VREFB1N2 IO VREFB1N2 M5 B1 VREFB1N2 IO DIFFIO_L16p L2 B1 VREFB1N2 IO DIFFIO_L16n L1 B1 VREFB1N2 IO DIFFIO_L17p M2 B1 VREFB1N2 IO DIFFIO_L17n M1 B1 VREFB1N2 IO DIFFIO_L18p P2 B1 VREFB1N2 IO DIFFIO_L18n P1 B1 VREFB1N2 IO N3 B1 VREFB1N2 IO DCLK P3 B1 VREFB1N2 IO DATA0 N7 B1 VREFB1N2 nCONFIG nCONFIG P4 B1 VREFB1N2 TDI TDI P7 B1 VREFB1N2 TCK TCK P5 B1 VREFB1N2 TMS TMS P8 B1 VREFB1N2 TDO TDO P6 B1 VREFB1N2 nCE nCE R8 B1 VREFB1N2 CLK0 DIFFCLK_0p J2 B1 VREFB1N2 CLK1 DIFFCLK_0n J1 B2 VREFB2N0 CLK2 DIFFCLK_1p Y2 B2 VREFB2N0 CLK3 DIFFCLK_1n Y1 B2 VREFB2N0 IO DIFFIO_L19p R2 B2 VREFB2N0 IO DIFFIO_L19n R1 B2 VREFB2N0 IO R6 B2 VREFB2N0 IO DIFFIO_L20p U3 B2 VREFB2N0 IO DIFFIO_L20n U4 B2 VREFB2N0 IO DIFFIO_L21p R3 B2 VREFB2N0 IO DIFFIO_L21n R4 B2 VREFB2N0 IO DIFFIO_L22p T4 B2 VREFB2N0 IO DIFFIO_L22n T3 B2 VREFB2N0 IO R5 B2 VREFB2N0 IO VREFB2N0 T7 B2 VREFB2N0 IO DIFFIO_L23p U2 B2 VREFB2N0 IO DIFFIO_L23n U1 B2 VREFB2N0 IO DIFFIO_L24p V4 B2 VREFB2N0 IO DIFFIO_L24n V3 B2 VREFB2N0 IO DIFFIO_L25p V2 B2 VREFB2N0 IO DIFFIO_L25n V1 B2 VREFB2N1 IO DPCLK1 DIFFIO_L26p AB2 B2 VREFB2N1 IO DIFFIO_L26n AB1 B2 VREFB2N1 IO DIFFIO_L27p W2 B2 VREFB2N1 IO DIFFIO_L27n W1 B2 VREFB2N1 IO DIFFIO_L28p U6 B2 VREFB2N1 IO DIFFIO_L28n U5 B2 VREFB2N1 IO DIFFIO_L29p Y4 B2 VREFB2N1 IO DIFFIO_L29n Y3 B2 VREFB2N1 IO DIFFIO_L30p AC2 B2 VREFB2N1 IO DIFFIO_L30n AC1 B2 VREFB2N1 IO DIFFIO_L31p AC3 B2 VREFB2N1 IO DIFFIO_L31n AD3 B2 VREFB2N1 IO DIFFIO_L32p AD2 B2 VREFB2N1 IO DIFFIO_L32n AD1 B2 VREFB2N1 IO AB3 B2 VREFB2N1 IO VREFB2N1 T8 B2 VREFB2N2 IO DIFFIO_L33p AA4 B2 VREFB2N2 IO DIFFIO_L33n AA3 B2 VREFB2N2 IO RUP1 U7 B2 VREFB2N2 IO RDN1 U8 B2 VREFB2N2 IO DIFFIO_L34p AE2 B2 VREFB2N2 IO DIFFIO_L34n AE1 B2 VREFB2N2 IO W3 B2 VREFB2N2 IO VREFB2N2 AB4 B2 VREFB2N2 IO CDPCLK1 DIFFIO_L35p AE3 B2 VREFB2N2 IO DIFFIO_L35n AF2 B2 VREFB2N2 IO AB6 B2 VREFB2N2 IO AB5 B3 VREFB3N2 IO DIFFIO_B1p AD5 B3 VREFB3N2 IO DIFFIO_B1n AE6 B3 VREFB3N2 IO DIFFIO_B2p AD4 B3 VREFB3N2 IO DIFFIO_B2n AF4 B3 VREFB3N2 IO DIFFIO_B3p AE4 B3 VREFB3N2 IO DIFFIO_B3n AG3 B3 VREFB3N2 IO CDPCLK2 AD7 B3 VREFB3N2 IO PLL1_CLKOUTp AE5 B3 VREFB3N2 IO PLL1_CLKOUTn AF5 B3 VREFB3N2 IO DIFFIO_B4p AH3 B3 VREFB3N2 IO DIFFIO_B4n AF3 B3 VREFB3N2 IO AF6 B3 VREFB3N2 IO VREFB3N2 Y10 B3 VREFB3N2 IO DIFFIO_B5p AG4 B3 VREFB3N2 IO DIFFIO_B5n AH4 B3 VREFB3N2 IO DIFFIO_B6p AD8 B3 VREFB3N2 IO DIFFIO_B6n AC7 B3 VREFB3N2 IO DIFFIO_B7p AG6 B3 VREFB3N2 IO DIFFIO_B7n AH6 B3 VREFB3N2 IO DIFFIO_B8p AB9 B3 VREFB3N2 IO DIFFIO_B8n AB8 B3 VREFB3N2 IO AD10 B3 VREFB3N1 IO DIFFIO_B9p AG7 B3 VREFB3N1 IO DIFFIO_B9n AH7 B3 VREFB3N1 IO DIFFIO_B10p AB7 B3 VREFB3N1 IO DIFFIO_B10n AC8 B3 VREFB3N1 IO DIFFIO_B11p AA8 B3 VREFB3N1 IO DIFFIO_B11n AA10 B3 VREFB3N1 IO DIFFIO_B12p AG8 B3 VREFB3N1 IO DIFFIO_B12n AH8 B3 VREFB3N1 IO DIFFIO_B13p AE7 B3 VREFB3N1 IO DIFFIO_B13n AF7 B3 VREFB3N1 IO AF9 B3 VREFB3N1 IO DIFFIO_B14p AE8 B3 VREFB3N1 IO DIFFIO_B14n AF8 B3 VREFB3N1 IO AE9 B3 VREFB3N1 IO VREFB3N1 AB11 B3 VREFB3N1 IO DPCLK2 DIFFIO_B15p AE10 B3 VREFB3N1 IO DIFFIO_B15n AF10 B3 VREFB3N1 IO DIFFIO_B16p AG10 B3 VREFB3N0 IO DIFFIO_B16n AH10 B3 VREFB3N0 IO DIFFIO_B17p AE12 B3 VREFB3N0 IO DIFFIO_B17n AF12 B3 VREFB3N0 IO DIFFIO_B18p AE11 B3 VREFB3N0 IO DPCLK3 DIFFIO_B18n AF11 B3 VREFB3N0 IO DIFFIO_B19p AC11 B3 VREFB3N0 IO DIFFIO_B19n AD11 B3 VREFB3N0 IO DIFFIO_B20p AG11 B3 VREFB3N0 IO DIFFIO_B20n AH11 B3 VREFB3N0 IO DIFFIO_B21p AE13 B3 VREFB3N0 IO DIFFIO_B21n AF13 B3 VREFB3N0 IO VREFB3N0 AB13 B3 VREFB3N0 IO AD12 B3 VREFB3N0 IO DIFFIO_B22p AE14 B3 VREFB3N0 IO DIFFIO_B22n AF14 B3 VREFB3N0 IO DIFFIO_B23p AG12 B3 VREFB3N0 IO DIFFIO_B23n AH12 B3 VREFB3N0 CLK15 DIFFCLK_6p AG14 B3 VREFB3N0 CLK14 DIFFCLK_6n AH14 B4 VREFB4N2 CLK13 DIFFCLK_7p AG15 B4 VREFB4N2 CLK12 DIFFCLK_7n AH15 B4 VREFB4N2 IO DIFFIO_B24p AC15 B4 VREFB4N2 IO DIFFIO_B24n AD15 B4 VREFB4N2 IO DIFFIO_B25p AE15 B4 VREFB4N2 IO DIFFIO_B25n AF15 B4 VREFB4N2 IO DIFFIO_B26p AG17 B4 VREFB4N2 IO DIFFIO_B26n AH17 B4 VREFB4N2 IO AF16 B4 VREFB4N2 IO DIFFIO_B27p AA16 B4 VREFB4N2 IO DIFFIO_B27n AB16 B4 VREFB4N2 IO VREFB4N2 AA15 B4 VREFB4N2 IO AE16 B4 VREFB4N2 IO DIFFIO_B28p AE17 B4 VREFB4N2 IO DPCLK4 DIFFIO_B28n AF17 B4 VREFB4N2 IO DIFFIO_B29p AG18 B4 VREFB4N2 IO DIFFIO_B29n AH18 B4 VREFB4N2 IO DIFFIO_B30p AG19 B4 VREFB4N2 IO DIFFIO_B30n AH19 B4 VREFB4N2 IO DIFFIO_B31p AC17 B4 VREFB4N2 IO DIFFIO_B31n AD17 B4 VREFB4N1 IO DIFFIO_B32p AG21 B4 VREFB4N1 IO DIFFIO_B32n AH21 B4 VREFB4N1 IO DPCLK5 DIFFIO_B33p AE18 B4 VREFB4N1 IO DIFFIO_B33n AF18 B4 VREFB4N1 IO DIFFIO_B34p AG22 B4 VREFB4N1 IO DIFFIO_B34n AH22 B4 VREFB4N1 IO DIFFIO_B35p AG23 B4 VREFB4N1 IO DIFFIO_B35n AH23 B4 VREFB4N1 IO DIFFIO_B36p AE19 B4 VREFB4N1 IO DIFFIO_B36n AF19 B4 VREFB4N1 IO DIFFIO_B37p AF24 B4 VREFB4N1 IO DIFFIO_B37n AF25 B4 VREFB4N1 IO DIFFIO_B38p AE20 B4 VREFB4N1 IO DIFFIO_B38n AF20 B4 VREFB4N1 IO AD18 B4 VREFB4N1 IO DIFFIO_B39p AE21 B4 VREFB4N1 IO DIFFIO_B39n AF21 B4 VREFB4N1 IO VREFB4N1 AC18 B4 VREFB4N0 IO RUP2 AA17 B4 VREFB4N0 IO RDN2 AB17 B4 VREFB4N0 IO DIFFIO_B40p AE25 B4 VREFB4N0 IO CDPCLK3 DIFFIO_B40n AF26 B4 VREFB4N0 IO DIFFIO_B41p AG25 B4 VREFB4N0 IO DIFFIO_B41n AH25 B4 VREFB4N0 IO DIFFIO_B42p AE22 B4 VREFB4N0 IO DIFFIO_B42n AF22 B4 VREFB4N0 IO DIFFIO_B43p AD25 B4 VREFB4N0 IO DIFFIO_B43n AE24 B4 VREFB4N0 IO VREFB4N0 AB20 B4 VREFB4N0 IO DIFFIO_B44p AC21 B4 VREFB4N0 IO DIFFIO_B44n AD21 B4 VREFB4N0 IO Y19 B4 VREFB4N0 IO PLL4_CLKOUTp AE23 B4 VREFB4N0 IO PLL4_CLKOUTn AF23 B4 VREFB4N0 IO AD24 B4 VREFB4N0 IO DIFFIO_B45p AG26 B4 VREFB4N0 IO DIFFIO_B45n AH26 B5 VREFB5N2 IO DIFFIO_R41n AC25 B5 VREFB5N2 IO DIFFIO_R41p AC24 B5 VREFB5N2 IO AB24 B5 VREFB5N2 IO RUP3 AA22 B5 VREFB5N2 IO RDN3 AB23 B5 VREFB5N2 IO CDPCLK4 AF27 B5 VREFB5N2 IO VREFB5N2 AA24 B5 VREFB5N2 IO DIFFIO_R40n AD26 B5 VREFB5N2 IO DIFFIO_R40p AC26 B5 VREFB5N2 IO DIFFIO_R39n AE28 B5 VREFB5N2 IO DIFFIO_R39p AE27 B5 VREFB5N2 IO DIFFIO_R38n AD28 B5 VREFB5N2 IO DIFFIO_R38p AD27 B5 VREFB5N2 IO DIFFIO_R37n Y24 B5 VREFB5N2 IO DIFFIO_R37p Y23 B5 VREFB5N1 IO DIFFIO_R36n AC28 B5 VREFB5N1 IO DIFFIO_R36p AC27 B5 VREFB5N1 IO DIFFIO_R35n AB26 B5 VREFB5N1 IO DIFFIO_R35p AB25 B5 VREFB5N1 IO DIFFIO_R34n AA26 B5 VREFB5N1 IO DIFFIO_R34p AA25 B5 VREFB5N1 IO DIFFIO_R33n AB28 B5 VREFB5N1 IO DIFFIO_R33p AB27 B5 VREFB5N1 IO DIFFIO_R32n Y26 B5 VREFB5N1 IO DIFFIO_R32p Y25 B5 VREFB5N1 IO DIFFIO_R31n W26 B5 VREFB5N1 IO DIFFIO_R31p W25 B5 VREFB5N1 IO DIFFIO_R30n W27 B5 VREFB5N1 IO DIFFIO_R30p W28 B5 VREFB5N1 IO DIFFIO_R29n V28 B5 VREFB5N1 IO DIFFIO_R29p V27 B5 VREFB5N1 IO VREFB5N1 U23 B5 VREFB5N1 IO DIFFIO_R28n V26 B5 VREFB5N1 IO DIFFIO_R28p V25 B5 VREFB5N0 IO DIFFIO_R27n V24 B5 VREFB5N0 IO DIFFIO_R27p V23 B5 VREFB5N0 IO DIFFIO_R26n U27 B5 VREFB5N0 IO DIFFIO_R26p T26 B5 VREFB5N0 IO DIFFIO_R25n U26 B5 VREFB5N0 IO DIFFIO_R25p U25 B5 VREFB5N0 IO VREFB5N0 U24 B5 VREFB5N0 IO DIFFIO_R24n U28 B5 VREFB5N0 IO DPCLK6 DIFFIO_R24p T25 B5 VREFB5N0 IO DEV_OE DIFFIO_R23n T22 B5 VREFB5N0 IO DEV_CLRn DIFFIO_R23p T21 B5 VREFB5N0 IO DIFFIO_R22n R26 B5 VREFB5N0 IO DIFFIO_R22p R25 B5 VREFB5N0 IO DIFFIO_R21n R28 B5 VREFB5N0 IO DIFFIO_R21p R27 B5 VREFB5N0 IO R24 B5 VREFB5N0 CLK7 DIFFCLK_3n Y28 B5 VREFB5N0 CLK6 DIFFCLK_3p Y27 B6 VREFB6N2 CLK5 DIFFCLK_2n J28 B6 VREFB6N2 CLK4 DIFFCLK_2p J27 B6 VREFB6N2 CONF_DONE CONF_DONE P24 B6 VREFB6N2 MSEL0 MSEL0 N22 B6 VREFB6N2 MSEL1 MSEL1 P23 B6 VREFB6N2 MSEL2 MSEL2 M22 B6 VREFB6N2 MSEL3 MSEL3 P22 B6 VREFB6N2 IO INIT_DONE DIFFIO_R20n P26 B6 VREFB6N2 IO CRC_ERROR DIFFIO_R20p P25 B6 VREFB6N2 IO M24 B6 VREFB6N2 IO VREFB6N2 N21 B6 VREFB6N2 IO nCEO DIFFIO_R19n P28 B6 VREFB6N2 IO CLKUSR DIFFIO_R19p P27 B6 VREFB6N2 IO DPCLK7 DIFFIO_R18n N26 B6 VREFB6N2 IO DIFFIO_R18p N25 B6 VREFB6N2 IO DIFFIO_R17n M28 B6 VREFB6N2 IO DIFFIO_R17p M27 B6 VREFB6N2 IO DIFFIO_R16n M26 B6 VREFB6N2 IO DIFFIO_R16p M25 B6 VREFB6N2 IO DIFFIO_R15n L28 B6 VREFB6N1 IO DIFFIO_R15p L27 B6 VREFB6N1 IO DIFFIO_R14n L24 B6 VREFB6N1 IO DIFFIO_R14p L23 B6 VREFB6N1 IO DIFFIO_R13n K28 B6 VREFB6N1 IO DIFFIO_R13p K27 B6 VREFB6N1 IO L26 B6 VREFB6N1 IO DIFFIO_R12n J26 B6 VREFB6N1 IO DIFFIO_R12p J25 B6 VREFB6N1 IO DIFFIO_R11n G28 B6 VREFB6N1 IO DIFFIO_R11p G27 B6 VREFB6N1 IO VREFB6N1 M21 B6 VREFB6N1 IO L25 B6 VREFB6N1 IO DIFFIO_R10n K26 B6 VREFB6N1 IO DIFFIO_R10p K25 B6 VREFB6N1 IO DIFFIO_R9n F28 B6 VREFB6N1 IO DIFFIO_R9p F27 B6 VREFB6N1 IO DIFFIO_R8n E28 B6 VREFB6N1 IO DIFFIO_R8p E27 B6 VREFB6N0 IO DIFFIO_R7n H26 B6 VREFB6N0 IO DIFFIO_R7p F26 B6 VREFB6N0 IO DIFFIO_R6n H25 B6 VREFB6N0 IO DIFFIO_R6p E26 B6 VREFB6N0 IO DIFFIO_R5n D28 B6 VREFB6N0 IO DIFFIO_R5p D27 B6 VREFB6N0 IO CDPCLK5 DIFFIO_R4n C27 B6 VREFB6N0 IO DIFFIO_R4p D26 B6 VREFB6N0 IO DIFFIO_R3n H24 B6 VREFB6N0 IO DIFFIO_R3p H23 B6 VREFB6N0 IO DIFFIO_R2n G26 B6 VREFB6N0 IO DIFFIO_R2p G25 B6 VREFB6N0 IO VREFB6N0 J22 B6 VREFB6N0 IO DIFFIO_R1n F25 B6 VREFB6N0 IO DIFFIO_R1p F24 B7 VREFB7N0 IO DIFFIO_T47n C26 B7 VREFB7N0 IO DIFFIO_T47p B26 B7 VREFB7N0 IO DIFFIO_T46n D22 B7 VREFB7N0 IO DIFFIO_T46p E22 B7 VREFB7N0 IO DIFFIO_T45n A26 B7 VREFB7N0 IO CDPCLK6 DIFFIO_T45p A25 B7 VREFB7N0 IO B25 B7 VREFB7N0 IO DIFFIO_T44n E21 B7 VREFB7N0 IO DIFFIO_T44p F21 B7 VREFB7N0 IO VREFB7N0 F22 B7 VREFB7N0 IO DIFFIO_T43n D25 B7 VREFB7N0 IO DIFFIO_T43p C25 B7 VREFB7N0 IO DIFFIO_T42n A23 B7 VREFB7N0 IO DIFFIO_T42p B23 B7 VREFB7N0 IO PLL2_CLKOUTn C23 B7 VREFB7N0 IO PLL2_CLKOUTp D23 B7 VREFB7N0 IO DIFFIO_T41n C24 B7 VREFB7N0 IO DIFFIO_T41p D24 B7 VREFB7N0 IO DIFFIO_T40n C22 B7 VREFB7N0 IO DIFFIO_T40p D21 B7 VREFB7N1 IO RUP4 F19 B7 VREFB7N1 IO RDN4 E19 B7 VREFB7N1 IO C21 B7 VREFB7N1 IO DIFFIO_T39n A22 B7 VREFB7N1 IO DIFFIO_T39p B22 B7 VREFB7N1 IO DIFFIO_T38n A21 B7 VREFB7N1 IO DIFFIO_T38p B21 B7 VREFB7N1 IO DIFFIO_T37n E18 B7 VREFB7N1 IO DIFFIO_T37p F18 B7 VREFB7N1 IO DIFFIO_T36n C18 B7 VREFB7N1 IO DIFFIO_T36p D18 B7 VREFB7N1 IO DIFFIO_T35n C20 B7 VREFB7N1 IO DIFFIO_T35p D20 B7 VREFB7N1 IO DIFFIO_T34n C19 B7 VREFB7N1 IO DIFFIO_T34p D19 B7 VREFB7N1 IO VREFB7N1 G17 B7 VREFB7N1 IO DIFFIO_T33n C17 B7 VREFB7N1 IO DPCLK8 DIFFIO_T33p D17 B7 VREFB7N1 IO DIFFIO_T32n A19 B7 VREFB7N1 IO DIFFIO_T32p B19 B7 VREFB7N2 IO DIFFIO_T31n A18 B7 VREFB7N2 IO DIFFIO_T31p B18 B7 VREFB7N2 IO DIFFIO_T30n F15 B7 VREFB7N2 IO DIFFIO_T30p G16 B7 VREFB7N2 IO DIFFIO_T29n E25 B7 VREFB7N2 IO DIFFIO_T29p E24 B7 VREFB7N2 IO DIFFIO_T28n F17 B7 VREFB7N2 IO DIFFIO_T28p G18 B7 VREFB7N2 IO E17 B7 VREFB7N2 IO VREFB7N2 G15 B7 VREFB7N2 IO DIFFIO_T27n C16 B7 VREFB7N2 IO DIFFIO_T27p D16 B7 VREFB7N2 IO DIFFIO_T26n A17 B7 VREFB7N2 IO DPCLK9 DIFFIO_T26p B17 B7 VREFB7N2 IO E15 B7 VREFB7N2 IO DIFFIO_T25n C15 B7 VREFB7N2 IO DIFFIO_T25p D15 B7 VREFB7N2 CLK8 DIFFCLK_5n A15 B7 VREFB7N2 CLK9 DIFFCLK_5p B15 B8 VREFB8N0 CLK10 DIFFCLK_4n A14 B8 VREFB8N0 CLK11 DIFFCLK_4p B14 B8 VREFB8N0 IO DIFFIO_T24n C13 B8 VREFB8N0 IO DIFFIO_T24p D13 B8 VREFB8N0 IO DIFFIO_T23n C14 B8 VREFB8N0 IO DIFFIO_T23p D14 B8 VREFB8N0 IO DIFFIO_T22n C12 B8 VREFB8N0 IO DPCLK10 DIFFIO_T22p D12 B8 VREFB8N0 IO DIFFIO_T21n A12 B8 VREFB8N0 IO DIFFIO_T21p B12 B8 VREFB8N0 IO VREFB8N0 G14 B8 VREFB8N0 IO DIFFIO_T20n F14 B8 VREFB8N0 IO DIFFIO_T20p E14 B8 VREFB8N0 IO DATA2 DIFFIO_T19n A11 B8 VREFB8N0 IO DATA3 DIFFIO_T19p B11 B8 VREFB8N0 IO DIFFIO_T18n A10 B8 VREFB8N0 IO DATA4 DIFFIO_T18p B10 B8 VREFB8N0 IO DIFFIO_T17n G13 B8 VREFB8N0 IO DIFFIO_T17p H13 B8 VREFB8N1 IO DIFFIO_T16n C10 B8 VREFB8N1 IO DIFFIO_T16p D10 B8 VREFB8N1 IO DPCLK11 DIFFIO_T15n E12 B8 VREFB8N1 IO DIFFIO_T15p F12 B8 VREFB8N1 IO DIFFIO_T14n E11 B8 VREFB8N1 IO DIFFIO_T14p F11 B8 VREFB8N1 IO DIFFIO_T13n A7 B8 VREFB8N1 IO DATA5 DIFFIO_T13p B7 B8 VREFB8N1 IO VREFB8N1 G12 B8 VREFB8N1 IO DIFFIO_T12n A6 B8 VREFB8N1 IO DATA6 DIFFIO_T12p B6 B8 VREFB8N1 IO DATA7 DIFFIO_T11n C11 B8 VREFB8N1 IO DIFFIO_T11p D11 B8 VREFB8N1 IO DIFFIO_T10n C9 B8 VREFB8N1 IO DIFFIO_T10p D9 B8 VREFB8N1 IO DIFFIO_T9n A8 B8 VREFB8N1 IO DIFFIO_T9p B8 B8 VREFB8N1 IO DIFFIO_T8n C8 B8 VREFB8N1 IO DIFFIO_T8p D8 B8 VREFB8N1 IO DIFFIO_T7n C7 B8 VREFB8N2 IO DIFFIO_T7p D7 B8 VREFB8N2 IO D6 B8 VREFB8N2 IO VREFB8N2 G9 B8 VREFB8N2 IO DIFFIO_T6n E10 B8 VREFB8N2 IO DIFFIO_T6p F10 B8 VREFB8N2 IO DIFFIO_T5n E8 B8 VREFB8N2 IO DIFFIO_T5p F8 B8 VREFB8N2 IO DIFFIO_T4n E5 B8 VREFB8N2 IO DIFFIO_T4p E7 B8 VREFB8N2 IO DIFFIO_T3n A4 B8 VREFB8N2 IO CDPCLK7 DIFFIO_T3p B4 B8 VREFB8N2 IO DIFFIO_T2n B3 B8 VREFB8N2 IO DIFFIO_T2p A3 B8 VREFB8N2 IO C6 B8 VREFB8N2 IO PLL3_CLKOUTn C5 B8 VREFB8N2 IO PLL3_CLKOUTp D5 B8 VREFB8N2 IO DIFFIO_T1n C4 B8 VREFB8N2 IO DIFFIO_T1p D4 B8 VREFB8N2 IO E4 GND K10 GND K12 GND K14 GND K16 GND K18 GND K20 GND L9 GND L11 GND L13 GND L15 GND L17 GND L19 GND M10 GND M12 GND M14 GND M16 GND M18 GND M20 GND N9 GND N11 GND N13 GND N15 GND N17 GND N19 GND P10 GND P12 GND P14 GND P16 GND P18 GND P20 GND R9 GND R11 GND R13 GND R15 GND R17 GND R19 GND T10 GND T12 GND T14 GND T16 GND T18 GND T20 GND U9 GND U11 GND U13 GND U15 GND U17 GND U19 GND V10 GND V12 GND V14 GND V16 GND V18 GND V20 GND W9 GND W11 GND W13 GND W15 GND W17 GND W19 GND AA2 GND AA27 GND AC6 GND AC9 GND AC13 GND AC16 GND AC20 GND AC23 GND AF1 GND AF28 GND AG2 GND AG5 GND AG9 GND AG13 GND AG16 GND AG20 GND AG24 GND AG27 GND B2 GND B5 GND B9 GND B13 GND B16 GND B20 GND B24 GND B27 GND C1 GND C28 GND F6 GND F9 GND F13 GND F16 GND F20 GND F23 GND H2 GND H27 GND J11 GND J18 GND K6 GND K23 GND N2 GND N6 GND N23 GND N27 GND T2 GND T6 GND T23 GND T27 GND W6 GND W23 GND Y11 GND Y18 GND H3 GND H4 GNDA1 AA9 GNDA2 H20 GNDA3 H9 GNDA4 AA20 VCCD_PLL1 Y9 VCCD_PLL2 J20 VCCD_PLL3 J9 VCCD_PLL4 Y20 VCCIO1 B1 VCCIO1 H1 VCCIO1 K5 VCCIO1 N1 VCCIO1 N5 VCCIO2 AA1 VCCIO2 AG1 VCCIO2 T1 VCCIO2 T5 VCCIO2 W5 VCCIO3 AA11 VCCIO3 AD6 VCCIO3 AD9 VCCIO3 AD13 VCCIO3 AH2 VCCIO3 AH5 VCCIO3 AH9 VCCIO3 AH13 VCCIO4 AA18 VCCIO4 AD16 VCCIO4 AD20 VCCIO4 AD23 VCCIO4 AH16 VCCIO4 AH20 VCCIO4 AH24 VCCIO4 AH27 VCCIO5 AA28 VCCIO5 AG28 VCCIO5 T24 VCCIO5 T28 VCCIO5 W24 VCCIO6 B28 VCCIO6 H28 VCCIO6 K24 VCCIO6 N24 VCCIO6 N28 VCCIO7 A16 VCCIO7 A20 VCCIO7 A24 VCCIO7 A27 VCCIO7 E16 VCCIO7 E20 VCCIO7 E23 VCCIO7 H18 VCCIO8 A2 VCCIO8 A5 VCCIO8 A9 VCCIO8 A13 VCCIO8 E6 VCCIO8 E9 VCCIO8 E13 VCCIO8 H11 NC AA5 NC AA6 NC AA7 NC AA12 NC AA13 NC AA14 NC AA19 NC AA21 NC AA23 NC AB10 NC AB12 NC AB14 NC AB15 NC AB18 NC AB19 NC AB21 NC AB22 NC AC10 NC AC12 NC AC14 NC AC19 NC AC22 NC AD14 NC AD19 NC AD22 NC AE26 NC C3 NC F7 NC G7 NC G8 NC G10 NC G11 NC G19 NC G20 NC G21 NC G22 NC G23 NC G24 NC H8 NC H10 NC H12 NC H14 NC H15 NC H16 NC H17 NC H19 NC H21 NC H22 NC J5 NC J6 NC J7 NC J10 NC J12 NC J13 NC J14 NC J15 NC J16 NC J17 NC J19 NC J23 NC J24 NC K7 NC K8 NC K21 NC K22 NC L6 NC L7 NC L8 NC L21 NC L22 NC M7 NC M8 NC M23 NC N8 NC P21 NC R7 NC R21 NC R22 NC R23 NC U21 NC U22 NC V5 NC V6 NC V7 NC V8 NC V21 NC V22 NC W4 NC W7 NC W8 NC W21 NC W22 NC Y5 NC Y6 NC Y7 NC Y12 NC Y13 NC Y14 NC Y15 NC Y16 NC Y17 NC Y22 NC L4 NC L3 NC AC4 NC AC5 VCCA1 Y8 VCCA2 J21 VCCA3 J8 VCCA4 Y21 VCCINT K9 VCCINT K11 VCCINT K13 VCCINT K15 VCCINT K17 VCCINT K19 VCCINT L10 VCCINT L12 VCCINT L14 VCCINT L16 VCCINT L18 VCCINT L20 VCCINT M9 VCCINT M11 VCCINT M13 VCCINT M15 VCCINT M17 VCCINT M19 VCCINT N10 VCCINT N12 VCCINT N14 VCCINT N16 VCCINT N18 VCCINT N20 VCCINT P9 VCCINT P11 VCCINT P13 VCCINT P15 VCCINT P17 VCCINT P19 VCCINT R10 VCCINT R12 VCCINT R14 VCCINT R16 VCCINT R18 VCCINT R20 VCCINT T9 VCCINT T11 VCCINT T13 VCCINT T15 VCCINT T17 VCCINT T19 VCCINT U10 VCCINT U12 VCCINT U14 VCCINT U16 VCCINT U18 VCCINT U20 VCCINT V9 VCCINT V11 VCCINT V13 VCCINT V15 VCCINT V17 VCCINT V19 VCCINT W10 VCCINT W12 VCCINT W14 VCCINT W16 VCCINT W18 VCCINT W20 Notes: "(1) If the p pin or n pin is not available for the package, the particular differential pair is not supported." "(2) For more information about pin definition and pin connection guidelines, refer to the " Cyclone 10 LP Device Family Pin Connection Guidelines.