Implement High-Performance DSP Designs

The latest version of DSP Builder features the advanced blockset capability that allows timing-driven Simulink synthesis. This technology lets you achieve high-performance design implementations, running at near-peak FPGA performance in a matter of minutes—compare that to the hours, if not days, required to hand-optimize HDL code.

With the DSP Builder Advanced Blockset, building high-performance complex digital signal processing (DSP) signal chains becomes as simple as 1-2-3:

  1. Set the required system level constraints—in this case the clock rate for a 6-channel, 128-tap FIR filter is specified at 403 MHz within Simulink.
  2. Choose the target FPGA family—because different device families might have different DSP block architecture, this information has to be incorporated by the synthesis tool.
  3. Click RUN.

Figure 1. Build a High-Performance Filter in Three Easy Steps

DSP Builder Advanced Blockset synthesizes the Simulink description of the signal chain—taking into account the system level timing constraints specified; in this case 403.2 MHz. Using the built-in timing models for each FPGA and the performance of the IP blocks, the tool adds pipeline registers and control logic as necessary to achieve the clock rate provided.

The result (shown in Figure 2) is a six-channel FIR filter with realized system performance of 408 MHz without touching the HDL code.

Figure 2. Automatically Generated Timing-Optimized HDL Code

This new capability is critical for designing multichannel signal processing data paths in applications, such as multi-carrier, multi-antenna RF processing in wireless applications.

It automatically adds pipelined stages and registers, and implements time division multiplexing to generate highly optimized designs for functions, such as digital upconverter (DUC), digital downconverter (DDC), crest-factor reduction (CFR), and digital predistortion (DPD). DSP Builder version 12.0 includes design examples for multi-antenna, multi-carrier WiMAX, and WCDMA DUC and DDC designs.