Model Based Solutions Resources
DSP Floating Point Resources
New digital signal processing (DSP) systems use floating-point solutions to achieve a high degree of numeric stability and dynamic range. Applications such as radar, advanced wireless antenna processing, and medical imaging are some examples that require floating-point capabilities in FPGAs. As FPGAs grow in size and capability, they are becoming the highest performing platform available for any type of floating-point DSP implementation.
Design Reference Papers and Webcasts
| Title | Description |
|---|---|
| BDTi's Independent Analysis of Floating-point DSP Design Flow and Performance on Intel® FPGAs 28-nm FPGAs (PDF) | Read an assessment of Intel® FPGAs floating-point solution by BDTi, an independent technology analysis firm. The assessment includes a matrix inversion floating-point design example and highlights the performance results and usability of the floating-point tool flow. |
| Correctly Rounded Floating-Point Division for DSP-Enabled FPGAs (PDF) | Read the award-winning paper from FPL 2012 discussing improved floating-point division architectures available in DSP Builder Advanced Blockset. |
| Using Floating-Point FPGAs for DSP in Radar (PDF) | This white paper describes the advantages of using floating-point processing in FPGAs for DSP in radar applications. |
| Optimize Motor Control Designs with an Integrated FPGA Design Flow (PDF) | This white paper describes a design flow that leverages the adaptability of Intel® FPGAs FPGAs, variable-precision DSP, and integrated system-level design tools for motor control designs. |
| Achieving One TeraFLOPS with 28 nm FPGAs (PDF) | This white paper describes how floating-point technology on FPGAs is not only practical today, but how processing rates of one teraFLOPS are feasible and can be implemented on a single FPGA die. |
| Taking Advantage of Advances in FPGA Floating-Point IP Cores (PDF) | This white paper discusses Intel® FPGA’s floating-point intellectual property (IP) cores that include basic, advanced, matrix-multiply, matrix-inversion, and fast Fourier transform (FFT) functions. |
| Hardware-Based Floating-Point Design Flow | This DesignCon 2011 paper discusses floating-point issues and presents an optimal implementation of floating-point processing. |
| Advantages of FPGA-Based Motor Control | This paper describes an FPGA-based motor control system. |
| Implementing Floating-Point DSP in an FPGA (Webcast) | With our new floating-point design flow, you can now easily implement floating-point DSP on Intel® FPGAs. This webcast gives an overview of how our design flow overcomes the challenges of floating-point implementation. |
| Digital Signal Processing for Radar Applications – lecture at IEEE Long Island, New York on March 15, 2011 | This seminar features a STAP pulsed Doppler Radar simulation using back-end FPGA implementation, which includes a model of a radar system environment, optimized implementation of STAP back-end processing, and FPGA implementation. |
| How to achieve 1 trillion floating-point operations-per-second in an FPGA | This article explains the charateristics of FPGAs that are lacking in microprocessors and how they can be leveraged to produce a more optimal and high-performance floating-point flow. |
| Radar Basics – Part 1 | This article is Part 1 of a series of a five-part article on radar basics. |
| Radar Basics – Part 2 | This article is Part 2 of a series of a five-part article on radar basics. |
| Radar Basics – Part 3 | This article is Part 3 of a series of a five-part article on radar basics. |
| Radar Basics – Part 4 | This article is Part 4 of a series of a five-part article on radar basics. |
| Radar Basics – Part 5 | This article is Part 5 of a series of a five-part article on radar basics. |