Amongst the many uncertainties on the financial sector horizon, there are two things we know for sure. One is that significant regulatory change is coming; the other is that those financial businesses who respond best to this change will prosper.
“It’s clear that CPUs need to be supplemented with some serious silicon support”
Arguably, it’s never been more important for financial institutions to react quicker and more effectively – faced with the task of juggling important tasks such as detailed risk analysis,
Which is where FPGAs come in – or, to give them their full title, Field Programmable Gate Arrays. To the uninitiated, FPGAs are silicon devices that can be dynamically reprogrammed with
“For example, you could configure the FPGA with the hardware to quickly calculate a complex mathematical function; you could even programme it with a GPU or microprocessor if you wanted to. You can trade off application performance against FPGA resource
As the article goes on to say, this means engineers can provide application workloads/solutions that are faster and less energy-hungry than equivalent software implementations running on a fixed function general-purpose CPU; FPGA workloads are highly
As Zammattio puts it: “This versatility enables you to provision fast processing power efficiency, and low-latency service – potentially lowering your total cost of ownership, and maximizing compute capacity within the power, space and cooling constraints of your data centers.”
Traditionally, FPGAs have proved difficult to programme but as the Computer Business Review article explains, a new suite of products from Intel is designed to solve this problem. For example, the Intel® Acceleration Stack for FPGAs is a new architecture that allows software developers to harness FPGAs much easier. A core component is its FPGA Interface Manager, which provides
In addition, Intel has adapted the OpenCL™ language, developed by the Khronos Consortium*, so that developers can now code FPGA hardware designs in the widely used C language. Allied to that, the company is also rapidly building an ecosystem of third-party partners that specialise in building
Using the Intel® Acceleration Stack for FPGAs, the silicon can be directly transacted on with thread-safe APIs – a data type or static method is thread-safe if it behaves correctly when used from multiple threads, regardless of how those threads are executed, and without demanding additional coordination from the calling code –from within virtual machines and containers. It can also run indirectly through standard libraries that have been extended to support functions implemented in FPGA based accelerator cards.
As Zammiatto concludes: “This relieves developers of the need to craft customized drivers and debugging interfaces or complex hardware design language code, enabling them to focus on their core expertise – algorithm development – and develop their solutions faster, and with greater confidence.”
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