FPGA Military, Aerospace, and Government Design

Creating Military Designs

Intel and its partners offer a wide range of tools to help you resolve common challenges for military designs and significantly shorten your design cycle. To learn more, browse through our available design examples, FPGA development kits, daughtercards, and intellectual property (IP) cores.

Design Examples

The following design examples contain highly parameterized designs with simulation or in-hardware implementation working with an Intel® FPGA development board. The design examples come with the source code, all the design files and, if desired, a training seminar.

For more information about design examples, please feel free to contact us: Contact Intel

Data Sheet

Description

Features

Applications

Publish Date

Digital Channelizer

Channelizer is a wideband receiver that splits a wide bandwidth into individual bands of interest. As a result of processing gain, low signal-to-noise ratio (SNR) signals can be reliably detected in individual subchannels.

    Programmable super sample rate fast Fourier transform (FFT) IP

    Programmable Poly-Phase Filter-Bank IP

    FFT Optimized for Real Input Samples

    JESD204B interface to Analog Devices* 3GSPS 14 bit dual channel analog-to-digital converter (ADC) AD9208

    Intel® Stratix® 10 FPGA

    Wideband communication systems

    Cable system

    Measurement equipment

September 2018

Monobit DRFM

Monobit Digital RF Memory design example demonstrates the usage of Intel® FPGA integrated high-speed transceivers as a wideband front-end stage.

    Monobit Receiver/transmitter

    12.5 GHz instantaneous bandwidth

    Digital dithering

    Digital channelizer

    Intel® Stratix® 10 FPGA

    Electronic countermeasures

    Signal intelligence (COMINT/ELINT)

    Communication systems

March 2017

Oversampled Channelizer

This design features a polyphase filter bank developed using a DSP Builder for Intel® FPGA design tool oriented for DSP developers. Data from On-chip Signal Generator is streamed into Channelizer block that includes Commutator, Polyphase Filters, Circular Shifter, and FFT block. Captured output of the Channelizer is uploaded to host and presented in viewers, while showing some key signal quality metrics.

Oversampled Channelizer design includes an On-chip Signal Generator, which can provide programmable stimulus to Channelizer system, making the design example run without external signal generator and ADC.

    Sampling Rate Support: 24GSPS

    Support 256 Channels

    Polyphase signal processing infrastructure

    Dynamic Spectrum/Spectrogram View

    Time domain waveform View

    RF Performance measurements

    On-chip Signal Generator

    Intel® Agilex™ FPGA Development Kit

    Radar and Electronic Countermeasures

    Test and Measurement equipment

    Communication Systems

June 2022

Gaussian Noise Generator (GNG)

This reference design includes the generation of a Wideband Gaussian Noise signal using a poly-phase approach. The subsequent signal processing enables you to populate only desired spectral bands with custom-defined magnitude for each band.

    Wideband Gaussian Noise source – 2.5 GHz

    Digital filter banks

    Fine spectral resolution < 2.5 MHz

    Dynamic band and magnitude control

    Floating-point processing in FPGA

    Intel® Arria® 10 FPGA

    AD9162 – 5GSPS digital-to-analog converter (DAC) with JESD204B interface

    Electronic countermeasures

    Radar

    Communication systems

    Hardware accelerated simulations

June 2016
Oversampling Channelizer with Spatial Overlapping This is a subset of wideband SSR oversampling channelizer. The implementation architecture of an oversampling channelizer can be very different depending on the input sample rate, number of channels, and number of overlapping samples. In this architecture, the number of FFT channels is low, the number of overlapping samples is less than the number of parallel paths. Overlapping inputs happen across the parallel paths, thus the term 'spatial overlapping'.

    Efficient parallel architecture

    Complex or real input

    Natural channel order output

    Operating clock independent of sampling rate

    Electronic countermeasures

    Radar

    Communication systems

February 2014

Adaptive Beamforming

MVDR adaptive beamformer example design shows efficient implementation of adaptive beamforming on Intel® FPGAs. Adaptive beamformer achieves optimal signal quality from desired direction, while suppressing the interferences from undesired direction. MVDR is based on Sample-Matrix-Inversion method, where the beamforming weights are calculated based on direct observation of the environment.

    MVDR algorithm

    Linear-phased array

    Array size 8 and 64

    Multi-beam adaptation

    Intel Code Builder for OpenCL™ application programming interface (API)

    Intel® Arria® 10 FPGA Development Kit

    Radar

    Sonar

    Electronic countermeasures

    Communication systems

    Microphone arrays

July 2019

Time Delay Digital Beamforming

The Time Delay Beamforming design example is implemented in the Stratix V DSP Development Kit. True time delay is achieved through a fractional delay filter with arbitrary fine resolution. The design example covers a simple but complete transmit and receive pulsed radar system with 32 phased array elements.

    Wideband beamforming

    Arbitrary steering angle

    Scalable design

    Active electronically scanned array (AESA)

    Radar, Sonar

    Phased array radio telescope

    Electronic countermeasures

February 2014

FFT Beamforming

The FFT beamforming demo generates multiple beams simultaneously for spatial filtering. This translates to better performance, which is an essential requirement for real-time systems.

    Programmable super sample rate FFT IP

    FFT beamforming targeting linear array

    FFT beamforming targeting planar array

    Radar

    Radiology

    Radio astronomy

April 2016

Pulse Doppler

This design example demonstrates Pulse Doppler processing. In typical radar application there is a requirement to calculate and identify Doppler frequencies. This is done by calculating FFT across multiple coherent radar pulses. Due to inherent write/read pattern of dynamic memories, the corner turn operation is inefficient. This design shows how to mitigate the throughput bottleneck as a result of corner turn.

    Efficient corner-turn implementation

    Fixed point and Floating point

    FFT example for Pulse Doppler

    Electronic countermeasures

    Radar

October 2016

Pulse Compression

In a typical pulsed radar, Pulse Compression correlates receive signal with a known waveform to increase the range resolution and SNR. This design example demonstrates Pulse Compression with Overlap-and-Save technique.

    Pulse radar range resolution increase

    Increase detection SNR

    FFT-based fast convolution

    Electronic countermeasures

    Radar

December 2013

Image Formation in Synthetic-Aperture Radar (SAR) Synthetic Aperture Radar (SAR) is a technique used in modern radars to acquire high-resolution images of scene. Intel® FPGAs are enabling such technology even under tight SWaP constrains.

    Global back-projection image formation

    Efficient and scalable array architecture

    Floating point on FPGA

    Intel® Stratix® 10 FPGA

    Synthetic Aperture Radar (SAR)

    Synthetic Aperture Sonar (SAS)

April 2018

Radar Waveform Classification

Intel Radar waveform classification example design is built to recognize unique micro-Doppler signatures of different targets using a convolution neural network (CNN) model.

    Micro-Doppler classification

    Real-time radar waveform recognition

    Intel Distribution of OpenVINO™ toolkit

    Intel® Arria® 10 FPGA Development Kit board

    Autonomous vehicles

    Surveillance radar for military

    Robotics

June 2018

Semantic Segmentation Using Deep Learning

Semantic Segmentation is used in a variety of self-navigating robotic applications. The application is to classify the type of object that each pixel in the image belongs to. This example shows the detection and segmentation of houses from overhead imagery.

    Mini U-Net-based semantic segmentation demo

    Intel® Arria® 10 FPGA Development Kit

    SpaceNet Dataset

    Intel Distribution of OpenVINO toolkit

    Deep learning

    Navigation

    Optical surveillance

    Satellite imaging

April 2018

Linear Solver with QR Decomposition

The QR Decomposition Solver design example is a parameterizable implementation designed to solve various matrix sizes. QR-based algorithm has good numerical stability and can solve rectangular, over-determined equation systems. The algorithm is one of the first complex floating-point reference designs highlighting feasibility and performance of floating-point IP on FPGA.

    Linear equation system solver

    Parameterizable and scalable IP

    Throughput acceleration

    Power efficiency

    Floating point

    Radar and sonar STAP algorithm

    Adaptive beamformer

    Scientific computing

    Adaptive filtering

April 2014

Linear Solver with Cholesky Decomposition

The Cholesky Decomposition Solver design example is a parameterizable implementation designed to solve various matrix sizes. Cholesky-based algorithm can solve private case of square equation system, in more efficient way than other algorithms like QR.

The algorithm is one of the first complex floating-point design examples highlighting feasibility and performance of floating-point IP on FPGA.

    Linear equation system solver

    Parameterizable and scalable IP

    Throughput acceleration

    Power efficiency

    Floating point

    Radar and sonar STAP algorithm

    Adaptive beamformer

    Scientific computing

    Adaptive filtering

February 2014

Extended Kalman Filter

The Extended Kalman Filter (EKF) is implemented on the Cyclone® V SoC. It efficiently utilizes a hybrid architecture, where a portion of the algorithm is offloaded to the FPGA fabric to increase overall system performance and offload the Arm* processor.

    Matrix co-processor IP

    Doubles CPU system performance†

    Compact FPGA footprint

    Cyclone V SoC

    Radar and sonar

    Guidance and navigation

    Inertial navigation sensors

    Sensor fusion

    Motor control

February 2014

Partition-Based Security

The Partition-Based Security design example demonstrates a secure way of assignment of security keys to multiple encrypted partial regions in the Intel® FPGA.

    Secure partial reconfiguration (PR)

    Simultaneous support for both one-time programmable (OTP) key and battery-backed key

    Qcrypt security tool

    PR configuration from EPCQ flash

    Intel® Arria® 10 FPGA with SoC Development Kit

    Data center/ multi-tenancy

    Automotive

    Secured communications commercial off-the-shelf (COTS) boards

    Applications requiring multi-level security

March 2017

Daughtercards

Intel and its partners offer a variety of application-specific daughtercards. You can use these daughtercards to expand the functionality of other development platforms. Design examples and application-specific software accompany many of the daughtercards, further facilitating the design process.