® Intel Xeon™ Processor with ® 512 KB L2 Cache and Intel E7500 Chipset Platform Design Guide

® 
Intel Xeon™ Processor with ® 
512 KB L2 Cache and Intel 
E7500 Chipset Platform 
Design Guide

® Intel Xeon™ Processor with ® 512 KB L2 Cache and Intel E7500 Chipset Platform Design Guide

March 2002 Document Number: 298649-002 ® Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel ...disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ® ® The Intel E7500 chipset and processors in the Intel Xeon processor family may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 2 2 I C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed by Intel. 2 Implementations of the I C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN and Alert on LAN2 are a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 Intel, Pentium, Intel Xeon, Intel Netburst and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2002, Intel Corporation Design Guide 2 Contents 1 2 3 4 5 Introduction ................................................................................................................15 1.1 Reference Documentation...................................................................................15 1.2 Conventions and Terminology.............................................................................17 1.3 System Overview ................................................................................................19 1.3.1 Intel® Xeon™ Processor with 512 KB L2 Cache ...............................20 1.3.2 Intel® E7500 Chipset .........................................................................21 1.3.2.1 Intel® E7500 Memory Controller Hub (MCH) .......................21 ® 1.3.2.2 I/O Controller Hub 3 (Intel ICH3-S).....................................22 ® 1.3.2.3 PCI/PCI-X 64-bit Hub 2 (Intel 82870P2 P64H2).................22 1.3.3 Bandwidth Summary ..........................................................................23 1.3.4 System Configurations .......................................................................23 Component Quadrant Layout..............................................................................25 2.1 Intel® Xeon™ Processor with 512 KB L2 Cache Quadrant Layout ....................26 2.2 Intel® E7500 MCH Quadrant Layout...................................................................27 ® 2.3 Intel ICH3-S Quadrant Layout...........................................................................28 ® 2.4 Intel 82870P2 P64H2 Quadrant Layout ............................................................29 Platform Stack-Up and Component Placement Overview.......................31 3.1 Platform Component Placement .........................................................................31 3.2 Platform Stack-Up ...............................................................................................32 Platform Clock Routing Guidelines ..................................................................35 4.1 Clock Groups.......................................................................................................38 4.1.1 HOST_CLK Clock Group ...................................................................38 4.1.1.1 HOST_CLK Clock Topology.................................................38 Read the full ® Intel Xeon™ Processor with ® 512 KB L2 Cache and Intel E7500 Chipset Platform Design Guide.

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