Intel® Arria® 10 FPGAs & SoCs
Highest Performance FPGA and SoC at 20 nm1
Intel® Arria® 10 FPGAs deliver more than a speed grade faster core performance and up to a 20% fMAX advantage compared to the competition, using publicly-available OpenCore designs.1 Intel® Arria® 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs and feature the industry’s only hard floating-point digital signal processing (DSP) blocks with speeds up to 1.5 tera floating-point operations per second (TFLOPS).1
The 20 nm ARM*-based Intel® Arria® 10 SoC delivers optimal performance, power efficiency, small form factor, and low cost for midrange applications. The Intel Arria 10 SoC, based on TSMC’s 20 nm process technology, combines a dual-core ARM Cortex*-A9 MPCore* Hard Processor System (HPS) with industry-leading programmable logic technology that includes hardened floating-point digital signal processing (DSP) blocks. The Intel Arria 10 SoC offers a processor with a rich feature set of embedded peripherals, hardened floating-point variable-precision DSP blocks, embedded high-speed transceivers, hard memory controllers, and protocol intellectual property (IP) controllers - all in a single highly integrated package.
Intel® Arria® 10 FPGAs & SoCs
Hard Processor System (HPS)
Intel® Arria® 10 SoCs feature a second-generation dual-core ARM* Cortex*-A9 MPCore* processor-based hard processor system (HPS) that is faster, more secure, and software compatible with previous-generation SoCs. With Intel® Arria® 10 SoCs you can reduce board size while increasing performance by integrating a GHz-class processor, FPGA logic, and digital signal processing (DSP) functions into a single user-customizable system on a chip. Intel® Arria® 10 SoCs offer the broadest selection of FPGA logic densities to date. These improvements address the performance, power, and security requirements of next-generation communications, broadcast, and computer and storage equipment.
Intel® Arria® 10 SoC Family HPS Features
The HPS is common to all the devices in the Intel® Arria® 10 SoC series.
Intel® Arria® 10 FPGA and SoC Transceiver Applications
Intel® Arria® 10 FPGA and SoC transceivers are well suited for:
- Remote radio heads.
- Nx100G data transmission.
- Server acceleration.
- 4K video processing.
- Military radar.
- And many more high-bandwidth applications.
- Built on 20 nm process technology, the Intel® Arria® 10 FPGAs and SoCs provide over 3.3 Tbps of total serial bandwidth. Intel® Arria® 10 GX devices offer up to 96 channels at 17.4 Gbps for short-reach applications as well as up to 12.5 Gbps for backplane support. In addition, the Intel® Arria® 10 GT FPGAs offers data rates up to 25.78 Gbps bringing high-end bandwidth performance into a midrange device.
Intel® Arria® 10 FPGA and SoC Transceiver Features
The Intel® Arria® 10 FPGA and SoC transceivers have a versatile feature set to handle a wide range of links and provide error-free link operation, including full-featured physical medium attachment (PMA) and hard physical coding sublayer (PCS) layers. In addition, dedicated PCI Express* (PCIe*) hard intellectual property (IP) blocks provide a full hardened protocol stack to support PCIe* Gen1, Gen2, and Gen3x8. The following figure shows the rich set of capabilities that are available to implement high-speed serial links with benefits described.
DSP Block Modes
The three DSP block modes available are as follows:
- Floating-point mode.
- Standard-precision mode.
- High-precision mode.
Hardened Floating-Point Processing in Intel® Arria® 10 FPGAs and SoCs
In Intel® Arria® 10 devices, Intel has enhanced the variable-precision DSP block by including hardened floating-point operators. The Intel® Arria® 10 FPGA and SoC variable-precision DSP block introduces a new floating-point mode that delivers breakthrough floating-point performance of up to 1.5 TeraFLOPs.
The architectural innovation in the implementation of IEEE 754 single-precision hardened floating-point DSP (digital signal processing) blocks in Intel® Arria® 10 FPGAs and SoCs enable processing rates up to 1.5 TFLOPs (Tera Floating-point Operations Per Second) and power efficiency up to 40 GFLOPs/Watt.
With the three modes available for Intel® Arria® 10DSP blocks: standard-precision fixed-point, high-precision fixed point and single-precision floating-point, designers can implement a variety of algorithms that require fixed point all the way to double-precision IEEE 754 compliant floating-point operations. Hardened floating-point processing offers designers the ability to implement algorithms in floating point with the similar performance and power efficiency as fixed point. This can be achieved without any power, area, or density compromises and with no loss of fixed-point features or functionality.
Intel® Arria® 10 FPGAs and SoCs are a compelling solution for industrial, wireless systems, compute intensive applications such as high-performance computing, machine learning, high-precision radars and data center acceleration applications.
A single DSP block in the floating-point mode provides an IEEE 754 single-precision floating-point multiplier and an IEEE 754 single-precision adder, delivering the highest floating-point performance on any FPGA in the market. These floating-point operators allow floating-point designs to be similar to traditional fixed-point designs, providing the benefits of floating-point at no additional cost for FPGA designers. Also, designers are able to remain in floating point, eliminating months of converting algorithms to fixed point and verifying the accuracy.
The floating-point mode offers:
- An IEEE 754 single-precision multiplier and IEEE 754 single-precision adder in each DSP block.
- Support for floating-point operations, such as: AxB, A+C, A-C, AxB+C, AxB-C, Acc=AxB+Acc.
- Vector operations to support convolution, dot products, and other linear algebra functions.
- Complex multiplication using fast Fourier transform (FFT).
In addition to floating-point capabilities, the new variable prevision block includes:
- Internal pipeline registers for faster fMAX and lower power consumption.
- 108 inputs, 74 outputs.
- 18x19 multiply mode, allowing the pre-adder to use two 18 bit inputs.
- Optional second accumulator (feedback register) for complex serial filtering.
- Dual 18x19 independent multipliers.
- Built-in 18 bit or 28 bit coefficient register banks, available with or without the pre-adder function.
All DSP block modes feature a 64 bit accumulator and each variable-precision DSP block comes with a 64 bit cascade bus. The cascade bus allows the implementation of even higher precision signal processing through cascading multiple blocks using a dedicated bus.
The variable-precision DSP architecture maintains backward compatibility. It can efficiently support existing 18 bit DSP applications, such as high-definition video processing, digital up-or down-conversion and multirate filtering.
A complete suite of tools to accelerate designer’s productivity include model-based, C-based, and HDL/IP-based design entry.
- DSP Builder for Intel® FPGAs (Simulink-based)
- Intel FPGA SDK for OpenCL™ (C-based)
- Intel® Quartus® Prime (HDL/IP-based)
Need even more floating-point performance? Intel® Arria® 10 designs offer a seamless design and device migration path to Stratix 10 devices offering up to 10 TFLOPS of performance. For more information, contact your local sales representative.
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Product and Performance Information
Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.
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