Arria® V FPGAS Features
|Feature||Arria® V GZ FPGA||Arria® V GT FPGA||Arria® V GX FPGA||Arria® V ST SoC||Arria® V SX SoC|
|DDR3 Memory Interface Speed||800 MHz||667 MHz||667 MHz||667 MHz||667 MHz|
|Hard Memory Controllers||-||4||4||4||4|
|Transceivers (Gbps)||12.5 Gbps||10.3125||6.5536||10.3125||6.5536|
|PCI Express® (PCIe*) Gen3/2/1 hardened IP block||1||-||-||-||-|
|PCIe* Gen2/1 hardened IP blocks(s)||-||2||2||2||2|
|Single Event Upset (SEU) Mitigation||x||x||x||x||x|
Arria® V Architecture
Each Arria® V FPGA transceiver consists of the Physical Media Attachment, Physical Coding Sublayer, and hardened IP blocks with added clocking flexibilities and more independent channels. Every channel has a full PMA and PCS along with a dedicated independent receive analog PLL CDR. To make it easier for designers to meet transceiver speeds up to 12.5 Gbps, drive up to 40" of backplane, and implement PCIe* Gen3, Arria® V GZ contains a number of additional features.
*Note: Arria® V GX, and GT do not have Adaptive LinearEQ, EyeQ, PCIe* Gen3 and select hardened IP that Arria® V GZ has.
Optimized for Low Power and Low System Cost
- A single 10.3125-Gbps channel will consume < 165 mW of power.
- A single 12.5-Gbps channel will consume < 200 mW of power.
Variable-Precision DSP Block
The variable-precision DSP block in Arria® V and Cyclone® V FPGAs are optimized to provide the following enhancements:
- 108 inputs, 74 outputs.
- 18x19 multiply mode, allowing the pre-adder to use two 18-bit inputs.
- Optional second accumulator (feedback register) for complex serial filtering.
- Dual 18x19 independent multipliers.
- No restriction on use of hard pre-adder and external coefficients in 18-bit mode.
- Each processor core includes:
- 32 KB of L1 instruction cache, 32 KB of L1 data cache
- Single- and double-precision floating-point unit and NEONTM media engine
- CoreSightTM debug and trace technology
- 512 KB of shared L2 cache with error correction code (ECC) support
- 64 KB of scratch RAM with ECC support
- Multiport SDRAM controller with support for DDR2, DDR3, and LPDDR2 as well as optional ECC support
- 8-channel direct memory access (DMA) controller
- QSPI flash controller
- NAND flash controller with DMA
- SD/SDIO/MMC controller with DMA
- 2x 10/100/1000 Ethernet media access control (MAC) with DMA
- 2x USB On-The-Go (OTG) controller with DMA
- 4x I2C controller
- 2x UART
- 2x serial peripheral interface (SPI) master peripherals, 2x SPI slave peripherals
- Up to 134 general-purpose I/O (GPIO)
- 7x general-purpose timers
- 4x watchdog timers
High-Bandwidth HPS-to-FPGA Interconnect Backbone
Although the HPS and the FPGA can operate independently, they are tightly coupled via a high-bandwidth system interconnect built from high-performance ARM* AMBA* AXI bus bridges. IP bus masters in the FPGA fabric have access to HPS bus slaves via the FPGA-to-HPS interconnect. Similarly, HPS bus masters have access to bus slaves in the FPGA fabric via the HPS-to-FPGA bridge. Both bridges are AMBA AXI-3 compliant and support simultaneous read and write transactions. An additional 32-bit light-weight HPS-to-FPGA bridge provides low latency interface between the HPS and peripherals in the FPGA fabric. Up to six FPGA masters can share the HPS SDRAM controller with the processor. Additionally, the processor can be used to configure the FPGA fabric under program control via a dedicated 32-bit configuration port.
- HPS-to-FPGA: configurable 32-, 64-, or 128-bit AMBA AXI interface optimized for high bandwidth
- FPGA-to-HPS: configurable 32-, 64-, or 128-bit AMBA AXI interface optimized for high bandwidth
- Lightweight HPS-to-FPGA: 32-bit AMBA AXI interface optimized for low latency
- FPGA-to-HPS SDRAM controller: configurable multi-port interfaces with 6 command ports, 4x 64-bit read data ports and 4x 64-bit write data ports
- ~32-bit FPGA configuration manager
The 28 nm Arria® V FPGA family offers the lowest power, highest bandwidth FPGAs for mid-range applications, such as remote radio units, 10G/40G line cards, and in-studio mixers. A comprehensive offering of five device variants allows designers to optimally choose a solution that meets their price, performance, and power requirements. See the tables below for an overview of the Arria® V FPGA and SoC family and package choices.
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