MAX® V CPLD Features

MAX® V devices are ideal for general-purpose and power- and space-constrained designs in many market segments, including wireline, wireless, industrial, consumer, computer and storage, broadcast, and military. MAX® V CPLDs are used for a wide variety of applications previously implemented in older generation ASICs, ASSPs, FPGAs, and discrete logic devices.

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Architecture

Leveraging the successful MAX® II architecture, MAX® V devices combine instant-on, non-volatile CPLD characteristics with advanced features typically found in FPGAs, such as phase-locked loops (PLLs), on-chip memory, and internal oscillators.

Designed for Low Cost

MAX® V CPLDs are built using a low-cost fab process combined with a selection of popular, low-cost packages. A pad-limited, staggered I/O pad arrangement results in a small die size, as well as a low-cost-per-I/O pin.

MAX® V Architecture

The groundbreaking MAX® V CPLD architecture (Figure 1) includes an array of logic elements (LEs grouped in logic array blocks (LABs)), memory resources (non-volatile flash and LE RAM), digital PLLs, global signals (clocks or control signals), and a generous amount of user I/Os. The MultiTrack interconnect is designed to maximize performance and minimize power by using the most efficient, direct connection from input to logic to output. Find more details about the MAX® V architecture in the MAX® V Device Family Data Sheet (PDF).

Designed in Concert with Quartus Prime Software

To simplify the design optimization process, the MAX® V CPLD architecture and Quartus® Prime software fitting algorithms were refined in concert to optimize tPD, tCO, tSU, and fMAX performance with pins locked down. As design functionality changes, Quartus Prime software enhances the ability to meet or exceed performance requirements using locked pin assignments and a push-button compilation flow. All MAX® V CPLDs are supported by the free Quartus® Prime Lite Edition software.

I/O Voltage Flexibility

The MAX® V CPLD architecture supports MultiVolt I/O functionality, allowing different I/O banks to operate with different I/O voltages to seamlessly connect to other devices. The device core is powered by a single 1.8-V external supply (VCCINT), providing CPLD functionality with low dynamic and stand-by power.

The smaller density products have two I/O banks, while the larger density products have four I/O banks. Each bank can be supplied with an independent VCCIO reference voltage.