What’s New: Switch to Intelligence with the Intel® Tofino™ 3 Intelligent Fabric Processor
The Intel® Tofino™ 3 Intelligent Fabric Processor (IFP) is based on P4-programmability and accelerates packet processing with up to 25.6 Tbps bandwidth. It optimizes power consumption for hyperscale use cases and accelerates machine learning (ML) for distributed training workloads. It also supports real-time in-band network telemetry (INT) spanning the Edge-to-Cloud spectrum.
As data growth accelerates and demanding distributed workloads proliferate, service providers and enterprises require their networks to work smarter. Intel® Intelligent Fabric Processors (Intel® IFPs) enhance Ethernet switching with intelligence, high-performance, and real-time edge-to-cloud telemetry for visibility and manageability. Driven by P4-programmability, machine learning (ML) workload acceleration and highly secure solutions, Intel® IFPs accelerate packet processing for edge and cloud data centers, high performance computing (HPC) and communications service providers moving to cloud technologies.
The products spotlighted here originated from the Intel acquisition of Barefoot Networks in June 2019. This move benefits Intel customers to meet the performance goals and ever-changing needs of network owners by supporting Intel’s focus on end-to-end connectivity and networking infrastructure leadership.
Intel® Tofino™ Series
Meet the skyrocketing demand for bandwidth and data availability with the world’s fastest P4-programmable Intelligent Fabric Processors.
Intel® Tofino™ 2
The next generation of programmable Ethernet switch, Intel® Tofino™ 2 is the best choice for meeting the needs of hyperscale data centers.
Built with the same architecture as Intel® Tofino™, it’s capable of delivering twice the bandwidth of its predecessor—up to 12.8 Tb/s.
Intel® Tofino™
Intel® Tofino™ is the world’s first end-user programmable Ethernet switch. It is built using a Protocol Independent Switch Architecture (PISA) and is P4-programmable. Intel® Tofino™ switches are available in a selection of SKUs to suit different applications and needs.
Intel® P4 Suite
Access a complete set of tools, APIs, and more to develop and optimize P4 software for Intel® Intelligent Fabric Processors. P4 is the only open source language designed for programmable packet processing devices.
Intel® P4 Studio
In a next-generation development environment, Intel® P4 Studio gives you a use case‒driven toolset that includes all the resources you need to quickly develop custom P4 software for Intel® Tofino™ Intelligent Fabric Processors. It’s flexible and hardened for multiple control-plane options and offers helpful production-ready data-plane implementations.
Intel® P4 Insight
Reduce the development time for networking solutions and fully optimize your network software with Intel® P4 Insight. This software provides powerful debugging tools and gives you a detailed dashboard view of your P4 program so you can see exactly how it’s mapped to hardware resources.
Intel® Deep Insight Network Analytics Software
Intel® Deep Insight Network Analytics Software enables real-time per-packet visibility into your network infrastructure. Monitor and analyze every packet drop. Detect and store anomalies and events for deeper historical analysis.
Highlighted Use Cases
Real-Time Network Telemetry
Collect end-to-end data on your network state in real time to monitor issues—including short-lived events—that cause data bottlenecks and network failures. This will allow your enterprise to fix configuration errors and optimize data routing to greatly improve network performance.
Layer 4 Load Balancer
Load-balancing efforts often need complex appliances that can be a burden on the network infrastructure. With Intel® Tofino™ and Intel® P4 programmability, load balancing can be done inside the switch, bridging the gap between multi terabit switches and gigabit servers and appliances.
In-Network DDoS Detection
Intel® Tofino™ Intelligent Fabric Processors can enable networks that detect DDoS attacks faster and mitigate them more effectively due to their exceptionally high performance, and because these tasks are performed in the network and don’t rely on other resources.
Additional Use Cases
- DNS caching
- Firewall
- Network packet broker
- Tunnel gateways
Intel® Connectivity Education Hub
Learn how the P4 programming language can transform your network infrastructure end to end. Browse academic courses, subscribe to advanced online videos, or join our research program. The education hub gives you the resources and skills to develop powerful and efficient networking solutions with our connectivity products.
FAQs
Frequently Asked Questions
Are programmable switch chips more expensive than legacy fixed-function ASICs?
No. ASIC cost is determined by die size. The Intel® Tofino™ die size is similar to the die of legacy fixed-function ASICs running at the same speed.
Do programmable switch chips consume more power than legacy fixed-function ASICs?
No. In fact, in many cases they consume less. For equivalent features and protocols, the power consumption is identical. In a programmable switch, you can turn off features you don’t need and reduce power or use smaller tables.
I heard a rule of thumb that says programmable switches are slower than legacy fixed-function switches. Is that true?
No. With Intel® Tofino™ and Intel® Tofino™ 2, we have shown that programmability does not come with a compromise on performance. Intel® Tofino™ and Intel® Tofino™ 2 can be fully programmed by users, using the P4 programming language, and can currently process up to 12.8 Tb/s.
Is P4 an open language, or is it controlled by Intel?
P4 is an Apache-licensed open source language owned by P4.org, an independent nonprofit. Any company, university, or individual can join P4.org free and contribute to the language, compiler, and tools. Intel is one of over 100 members of P4.org, including companies from all across our industry, from AT&T to ZTE, and some of the world’s top universities. The P4.org Advisory Board consists of Amin Vahdat (Google), Jennifer Rexford (Princeton), Nate Foster (Cornell), Guru Parulkar (ONF), and Nick McKeown (Stanford/Intel). The language was designed by world experts in programming language design from Princeton, Cornell, Stanford, VMware, Intel, Microsoft, Xilinx, Barefoot, and Google. P4 is open source and owned by everyone. The language is carefully designed to be target independent and can be used to program any programmable forwarding device. So far, it has been used to program a variety of software and hardware switches and NICs from different sources. See P4.org for more details.
Will P4 replace OpenFlow?
P4 is more general than OpenFlow, allowing users to define exactly how the forwarding plane processes packets. OpenFlow can be expressed in the P4 language; openflow.p4 provides a helpful way to get started.
I am evaluating an Intel® Tofino™-based switch for my next-generation data center project. I have specific scalability requirements, which I want to compare against a data sheet. What are the table sizes for typical network functions such as L2, L3 host rules, L3 longest prefix match (LPM), and ACL?
This is a very valid question for a switch that is based on a fixed-function ASIC. Intel® Tofino™ is highly programmable, consisting of multiple pipelines and Match Action Units (MAU) inside each pipeline. An MAU contains a flexible parsing logic and multiple SRAM and TCAM table blocks that can be carved to accommodate a specific deployment. Intel can provide sample verified scalability numbers based on a reference P4 program and under NDA. However, they should never be interpreted as maximum theoretical scalability values of the chip.
What are the typical use cases I can get started with?
Programmability enables limitless flexibility and multiple use cases, ranging from the customization of the switch table sizes for efficient scale to the enhancement of the existing networking functions and the addition of new capabilities such as telemetry, security, and load balancing.
I am an end user who is talking to a switch ODM/OEM/OS vendor about support on a new protocol or encapsulation and I am being told that this can only come in a next-generation ASIC. Can Intel® Tofino™ help?
Absolutely! You should ask your vendor about their support for Intel® Tofino™ in their switching platform. Once the Intel® Tofino™-based platform is offered, you should be in full power to make data-plane feature requests and expect a feature delivery road map on the existing ASIC.
Is P4 an open language, or is it controlled by Intel?
P4 is an Apache-licensed open source language owned by P4.org, an independent nonprofit. Any company, university, or individual can join P4.org free and contribute to the language, compiler, and tools. Intel is one of over 100 members of P4.org, including companies from all across our industry, from AT&T to ZTE, and some of the world’s top universities. The P4.org Advisory Board consists of Amin Vahdat (Google), Jennifer Rexford (Princeton), Nate Foster (Cornell), Guru Parulkar (ONF), and Nick McKeown (Stanford/Intel). The language was designed by world experts in programming language design from Princeton, Cornell, Stanford, VMware, Intel, Microsoft, Xilinx, Barefoot, and Google. P4 is open source and owned by everyone. The language is carefully designed to be target independent and can be used to program any programmable forwarding device. So far, it has been used to program a variety of software and hardware switches and NICs from different sources. See P4.org for more details.
Will P4 replace OpenFlow?
P4 is more general than OpenFlow, allowing users to define exactly how the forwarding plane processes packets. OpenFlow can be expressed in the P4 language; openflow.p4 provides a helpful way to get started.
I am evaluating an Intel® Tofino™-based switch for my next-generation data center project. I have specific scalability requirements, which I want to compare against a data sheet. What are the table sizes for typical network functions such as L2, L3 host rules, L3 longest prefix match (LPM), and ACL?
This is a very valid question for a switch that is based on a fixed-function ASIC. Intel® Tofino™ is highly programmable, consisting of multiple pipelines and Match Action Units (MAU) inside each pipeline. An MAU contains a flexible parsing logic and multiple SRAM and TCAM table blocks that can be carved to accommodate a specific deployment. Intel can provide sample verified scalability numbers based on a reference P4 program and under NDA. However, they should never be interpreted as maximum theoretical scalability values of the chip.
What are the typical use cases I can get started with?
Programmability enables limitless flexibility and multiple use cases, ranging from the customization of the switch table sizes for efficient scale to the enhancement of the existing networking functions and the addition of new capabilities such as telemetry, security, and load balancing.
I am an end user who is talking to a switch ODM/OEM/OS vendor about support on a new protocol or encapsulation and I am being told that this can only come in a next-generation ASIC. Can Intel® Tofino™ help?
Absolutely! You should ask your vendor about their support for Intel® Tofino™ in their switching platform. Once the Intel® Tofino™-based platform is offered, you should be in full power to make data-plane feature requests and expect a feature delivery road map on the existing ASIC.
Resources
Documentation
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