Status
Launched
Launch Date
2013
Lithography
14 nm

Resources

Logic Elements (LE)
378000
Adaptive Logic Modules (ALM)
128160
Adaptive Logic Module (ALM) Registers
512640
Fabric and I/O Phase-Locked Loops (PLLs)
8
Maximum Embedded Memory
32 Mb
Digital Signal Processing (DSP) Blocks
648
Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP), Floating Point (hard IP)
Hard Processor System (HPS)
Quad-core 64-bit ARM* Cortex*-A53
Hard Memory Controllers
Yes
External Memory Interfaces (EMIF)
DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys

I/O Specifications

Maximum User I/O Count
392
I/O Standards Support
3.0 V to 3.3 V LVTTL, 1.2 V to 3.3V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL
Maximum LVDS Pairs
120
Maximum Non-Return to Zero (NRZ) Transceivers
24
Maximum Non-Return to Zero (NRZ) Data Rate
28.3 Gbps
Transceiver Protocol Hard IP
PCIe Gen3, 100G Ethernet

Advanced Technologies

Hyper-Registers
Yes
FPGA Bitstream Security
Yes

Package Specifications

Package Options
F1152

Supplemental Information

Additional Information