Status
Launched
Launch Date
Q2'19
Lithography
10 nm

Resources

Logic Elements (LE)
1918975
Adaptive Logic Modules (ALM)
650500
Adaptive Logic Module (ALM) Registers
2602000
Fabric and I/O Phase-Locked Loops (PLLs)
15
Maximum Embedded Memory
204 Mb
Digital Signal Processing (DSP) Blocks
1354
Digital Signal Processing (DSP) Format
Fixed Point (hard IP), Floating Point (hard IP), Multiply, Multiply and Accumulate, Variable Precision
Hard Processor System (HPS)
Quad-core 64 bit Arm* Cortex*-A53
Hard Crypto Blocks
2
Hard Memory Controllers
Yes
External Memory Interfaces (EMIF)
DDR4, QDR IV

I/O Specifications

Maximum User I/O Count
480
I/O Standards Support
1.2 V LVCMOS, 1.8 V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, True Differential Signaling
Maximum LVDS Pairs
240
Maximum Non-Return to Zero (NRZ) Transceivers
24
Maximum Non-Return to Zero (NRZ) Data Rate
28.9 Gbps
Maximum Pulse-Amplitude Modulation (PAM4) Transceivers
12
Maximum Pulse-Amplitude Modulation (PAM4) Data Rate
57.8 Gbps
Transceiver Protocol Hard IP
PCIe Gen4, 10/25/100G Ethernet

Advanced Technologies

Hyper-Registers
Yes
FPGA Bitstream Security
Yes

Package Specifications

Package Options
R2581A

Supplemental Information

Additional Information