The FPGA SmartNIC for Network Acceleration

  • Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000 is a highly customizable SmartNIC platform for multi-workload networking infrastructure and application acceleration. It has the right memory mixture designed for network functions, with integrated network interface card (NIC) in a small form factor that enables high throughput, low latency, low power/bit for custom networking pipeline. 
  • The Intel FPGA PAC N3000 product family include a variant that is designed to be Network Equipment Building System (NEBS)-friendly, for use in NEBS-compliant systems. To help protect systems from FPGA-hosted security exploits, the Intel FPGA PAC N3000 features a Root-of-Trust device that enables more secure loading of authorized workloads and board updates, and enforces policies to help prevent unauthorized access to critical board interfaces and flash memory. End-to-end industry standard and open source tool support allow users to quickly adapt to evolving workloads and industry standards.
  • Intel is accelerating 5G and network functions virtualization (NFV) adoption for ecosystem partners, such as Telecom Equipment Manufacturers (TEMs), Virtual Network Function (VNF) vendors, system integrators, and telcos to bring scalable and high-performance solutions to market. 

Network Functions Virtualization (NFV) Workloads Enabled by Intel® FPGA PAC N3000


Provider FPGA Advantage Additional Resources


F5 Networks

Up to 300X capacity to absorb distributed denial-of-service (DDoS) attacks


HCL Technologies

Up to 300% performance improvements for small packets
OVS Intel/HCL Technologies Full performance for 2x25G at 512B and above
Contrail Juniper / HCL 2x25 Gbps, 22 Mpps @ 64B
  • Contact Intel for the design example

vRan (Turbo 4G)

Intel/ HCL

Support up to 27 Gbps Uplink and 3 Gbps Downlink with up to 8 virtual machines (VMs) running in host

vRan (LDPC 5G)

Intel/ HCL

Support up to 15 Gbps Uplink and 5 Gbps Downlink with up to 8 VMs running in host

ORAN 7.2 Split Fronthaul

Intel/ HCL

Compression algorithms including Mu-Law and BFP

  • Contact Intel for the design example
vRAN (Turbo/LDPC + FH) Altiostar Complete vRAN Solution with combined FEC acceleration and fronthaul

Note: See Additional Resources for supporting data.  For more complete information about performance and benchmark results, visit