How do Cyclone II FPGAs compare with Cyclone FPGAs?
Cyclone II FPGAs offer lower prices and higher densities than the first-generation Cyclone FPGAs. Cyclone II FPGAs are built on 90-nm process technology, while the Cyclone family uses 0.13 µm. The second-generation devices also offer more features such as: embedded multipliers, more PLLS, support for more I/O standards, and interface to newer memory devices.
How do Cyclone II FPGAs compare to Stratix II FPGAs?
The Cyclone II and Stratix® II FPGA families were built to address different market needs. The basic building block for the Stratix II FPGA family is the adaptive logic module (ALM), while Cyclone II FPGAs use LEs consisting of 4-input look-up tables (LUT) and registers as the basic building blocks. However, Cyclone II FPGAs share some similarities with Stratix II FPGAs, such as:
- Core voltage: 1.2 V
- Process: 90-nm low-k dielectric process technology
- Memory blocks: 4-Kbit memory blocks (M4K RAM blocks)
Why is there a density overlap between Cyclone II and the Stratix II FPGAs?
The density overlap between the two families exists because of the need to address different market requirements. Stratix II FPGAs are high-performance and high-density FPGAs with robust features for high-end applications. As the industry's lowest-cost FPGAs, Cyclone II FPGAs aptly include features and capabilities that target high-volume applications where cost is the most critical factor.
Are Cyclone II FPGAs pin-compatible with Cyclone FPGAs?
No, Cyclone II FPGAs are not pin-compatible with Cyclone FPGAs. Cyclone II design goals prioritized low cost as the primary objective. Pin compatibility between families adds undesirable die size.
How many power supplies do you need on board for Cyclone II FPGAs?
Unlike competing FPGAs that require three power supplies, Cyclone II FPGAs simplify power management in a system by requiring only two: one for VCCINT (1.2 V) and one for VCCIO (3.3 V, 2.5 V, 1.8 V, or 1.5 V) that is user-controllable.
What type of embedded multipliers do Cyclone II FPGAs have?
Cyclone II FPGAs offer up to 150 embedded 18 x 18 multipliers capable of running at 250 MHz. The embedded multipliers can also be configured as two 9 x 9 multipliers, offering up to 300 9x9 multipliers. These multipliers are capable of efficiently implementing multiplication operations commonly found in digital signal processing (DSP) applications. Embedded multipliers in Cyclone II FPGAs can boost overall system performance and decrease system costs for cost-sensitive DSP applications.
What type of embedded memory and memory features do Cyclone II FPGAs have?
The Cyclone II embedded memory consists of columns of 4-Kbit M4K RAM blocks, each capable of data transfer rates of over 250 MHz. Each M4K RAM block can implement various types of memory, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Each block also includes extra parity bits for error control, mixed-width mode, and mixed-clock mode support.
System Clock Management
What type of system clock management solution is offered in Cyclone II FPGAs?
Cyclone II FPGAs provide a global clock network and PLLs with on- and off-chip capabilities for a complete system clock management solution. Cyclone II FPGAs have up to sixteen dedicated clock input pins that feed the global clock network lines directly.
What does the global clock network consist of, and what can it be used for in Cyclone II FPGAs?
The global clock network in Cyclone II FPGAs consists of sixteen global clock lines accessible throughout the entire device. It is optimized to minimize skew, providing clock, clear, and reset signals to all resources within the device.
How many PLLs are available in Cyclone II FPGAs? What PLL features are available?
Cyclone II FPGAs offer up to four PLLs. These PLLs provide general-purpose clocking management capabilities such as multiplication and phase shifting, programmable duty cycle, programmable bandwidth, spread spectrum input clocking, lock detection, as well as outputs for differential I/O pin support. The external clock outputs (one per PLL) can be used to provide clocks to other devices in the system, eliminating the need for other clock-management devices on the board.
I/O Standards & Memory Interfaces
Which external memory interfaces do Cyclone II FPGAs support?
Cyclone II FPGAs support dedicated, speed-optimized circuitry to interface with single data rate (SDR), double data rate (DDR) and DDR2 SDRAM devices and QDRII SRAM devices. Table 3 shows the clock speed and maximum data transfer rate for each memory interface.