DDR5 and DDR4 EMIF Intel® FPGA IP
DDR5 and DDR4 offer higher performance, density and lower power and more control features compared to DDR3. Intel FPGA DDR5 and DDR4 EMIF IP offers solutions for high computing memory needs for client and data center systems.
DDR5 and DDR4 EMIF Intel® FPGA IP
Intel Agilex® 7 FPGAs & SoCs, Intel® Stratix® 10 FPGAs & SoC and Intel® Arria® 10 FPGAs implement DRAM hardened memory controller & PHY. Hardening the controller & PHY offers several advantages which include:
- Shorter development cycles and faster time to market due to pre-closed timing
- More FPGA fabric logic resources available for user application
- Improved fmax, efficiency and latency
- Low power solution
EMIF Protocols & Features
Feature |
Intel Agilex® 5 FPGAs |
Intel Agilex® 7 FPGA M-Series |
Intel Agilex® 7 FPGA I- and F- Series |
Intel® Stratix® 10 FPGA |
---|---|---|---|---|
DDR5 |
Yes |
Yes |
No |
No |
LPDDR5 |
Yes |
Yes |
No |
No |
DDR4 |
Yes |
Yes |
Yes |
Yes |
LPDDR4 |
Yes |
Yes |
No |
No |
QDRIV |
Yes |
Yes |
Yes |
Yes |
Max Interface Width |
X72(DDR4) |
X80(DDR5) |
X72(DDR4) |
X72(DDR4) |
Maximum Interface Rate |
4667 Mbps (LPDDR5) |
5600 Mbps (DDR5) |
3200 Mbps (DDR4) |
2666 Mbps (DDR4) |
Maximum Ranks Supported |
2 |
2 |
4 |
4 |
Debug Features
EMIF Debug toolkit features include the below basic and advanced debug capabilities:
- Viewing calibration margin, status, pin delay & VREF settings
- Re-running calibration, traffic generator, driver margining
- Updating delay settings, termination settings
- Configurable Traffic Generator to send test traffic patterns
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