Our EDA ecosystem ensures that you have a complete design solution in designing, verifying, and integrating Intel® FPGAs into your systems.
EDA Partners
System-Level Design Partners
EDA Vendor | Product Name | Design Solution |
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Altium | Altium Designer | High-level design tool |
Agnisys Technology Pvt Ltd | IDesignSpec | Register map management |
Bluespec | Bluespec Compiler | High-level synthesis |
Cadence Design Systems,Inc. | C-to-Silicon Compiler | High-level synthesis |
Duolog Technologies | Socrates | Register map management |
Impulse Accelerated Technologies | ImpulseC CoDeveloper | High-level synthesis and simulation |
NEC | CyberWorkBench | High-level synthesis |
PDTi | SpectaReg | Register map management |
Poseidon Design Systems | Triton Tuner | System-level simulation |
Triton Builder | High-level synthesis | |
SynaptiCAD | TestBencher Pro | High-level design tool |
Design Creation Partners
EDA Vendor | Product Name | Design Solution |
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Mentor Graphics® | HDL Designer | Project management, design entry, and analysis tool |
Sigasi | Sigasi HDT | Design entry, code comprehension, project management, and collaboration |
Synthesis Partners
EDA Vendor | Product Name | Design Solution |
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Logic synthesis |
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Advanced logic synthesis |
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Timing closure tool |
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Logic synthesis tool |
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Timing closure tool |
Simulation Partners
EDA Vendor | Product Name | Design Solution |
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Simulation |
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Simulation |
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Cadence Design Systems,Inc. | Simulation |
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Simulation |
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Simulation |
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Symphony EDA | VHDL Simili | Simulation |
SynaptiCAD | VeriLogger Extreme | Simulation |
Synopsys | Simulation |
Verification Partners
EDA Vendor | Product Name | Design Solution |
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Aldec, Inc. | ALINT-PRO | Design Rule Checking and Clock Domain Crossing (CDC) Verification |
Analyze RTL | RTL checker |
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Create Timing Constraints | Constraints generator |
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Clock Domain Crossing (CDC) Verification | Clock Domain Crossing (CDC) | |
Cadence Design Systems,Inc. | Encounter Conformal Equivalence Checker | Formal verification |
EMA Design Automation | TimingDesigner | Timing verification |
Focus | Constraints generator |
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Confirm | Timing-exception verification |
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ReConfirm | Timing-exception validation |
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FormalPro | Equivalence checking |
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Questa Formal Verification | Functional verification |
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Questa Clock-Domain Crossing Verification | Clock domain crossing verification |
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Real Intent | Meridian CDC | Clock domain crossing verification |
TestBencher Pro | Testbench generator |
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WaveFormer Pro | Timing verification |
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SpyGlass for FPGA | RTL analysis for FPGA designs | |
SpyGlass Lint | Lint checks | |
SpyGlass CDC | Clock domain crossing (CDC) verification |
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VC Formal | Functional property verification | |
Formality | Logic equivalence checking | |
Dialite – Platform Edition | In-system verification and integrated RTL debug |
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AMBA Bus Verification | In-system verification |
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Specification checker |
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RTL checker |
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Finite state machine (FSM) coverage tool |
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Code coverage tool for simulation and testbench generation |
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RTL checker for simulation coverage |
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RTL checker for functional verification coverage |
Board-Level Design Partners
EDA Vendor | Product Name | Design Solution |
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Agilent Technologies | Advanced Design System (ADS) | Signal integrity (SI) analysis |
Altium | Altium Designer | PCB board schematics and layout |
Allegro FPGA System Planner | FPGA I/O planning |
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OrCAD FPGA System Planner | FPGA I/O planning |
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Allegro PCB SI | SI analysis |
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OrCAD Signal Explorer | SI analysis |
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Allegro Design Authoring Allegro Design Entry Capture / Capture CIS |
PCB board schematics |
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Cadence OrCAD Capture and Capture CIS | PCB board schematics |
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Allegro PCB Designer | PCB board layout |
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OrCAD PCB Designer | PCB board layout |
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I/O Designer | FPGA I/O planning |
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HyperLynx Signal Integrity (SI) | SI analysis |
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DxDesigner | PCB board schematics |
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PADS | PCB board schematics and layout |
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Expedition Enterprise | PCB board layout |
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Board Station | PCB board layout |
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Signal Integrity Software, Inc. (SiSoft) |
Quantum-SI | SI analysis |
Synopsys | HSPICE | SI analysis |
CR-5000 | PCB board schematics and layout |
All EDA Partners
ACCESS Program Partner | System- Level Design | Design Creation | Synthesis | Simulation | Verification | Board-Level Design | ASIC Prototyping | Design Optimization |
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Aldec, Inc. | ||||||||
Agilent Technologies | ||||||||
Agnisys Technology Pvt Ltd | ||||||||
Altium | ||||||||
Atrenta | ||||||||
Blue Pearl | ||||||||
Bluespec | ||||||||
Cadence Design Systems,Inc. | ||||||||
Duolog Technologies | ||||||||
EMA Design Automation | ||||||||
FishTail | ||||||||
Impulse Accelerated Technologies |
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NEC | ||||||||
PDTi | ![]() |
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Plunify | ![]() |
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Poseidon Design Systems | ![]() |
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Real Intent | ||||||||
Sigasi | ||||||||
Signal Integrity Software, Inc. (SiSoft) | ![]() |
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Synopsys® | ![]() |
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Zuken | ![]() |