Intel® Agilex™ SoC FPGA Hard Processor System (HPS) Overview (OEMBAGIL)

15 Minutes Online Course

Course Description

In this training you will learn about the architecture of the Intel® Agilex™ 10 SoC FPGA. You will learn about the Hard Processor System (HPS) and its contents. We begin by discussing the ARM* Cortex*-A53 MPU (Multi-Processor Unit). The Cache Coherency Unit (CCU) and System MMU (SMMU) memory management blocks are explained next. The bridges between the HPS, FPGA, and SDRAM are also discussed. The peripherals of the HPS are discussed including: UART, I2C, DMA, Ethernet MAC, and USB.

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At Course Completion

You will be able to:

    > Understand the architecture of the Intel Agilex SoC FPGA HPS

    > Understand the CCU and SMMU memory management blocks

    > List the bridges available in the Intel Agilex SoC FPGA

    > List the blocks of the HPS in the Intel Agilex SoC FPGA

Skills Required

    > Basic knowledge of computer architecture

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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