Partial Reconfiguration

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function. Create multiple personas for a particular region in your design without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA resources. PR enables the implementation of more complex FPGA systems.

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Application examples are shown in the simplified illustrations below. Figure A shows an application for algorithm acceleration, and Figure B shows a telecom application in optical networking. In both cases, the FPGA is reconfigured to implement different functions – a different algorithm in the case of algorithm acceleration, or a different client protocol in the telecom application (an optical networking muxponder). The key benefit here is that the rest of the FPGA continues to function.

Key Features

  • Speed up in partial reconfiguration time for Intel® Stratix® 10 devices
  • Push-button PR flow for faster time to market
  • Compliments existing script-based flow
  • Command line and graphical user interface for compilation and analysis
  • Hierarchical partial reconfiguration that allows you to create child PR partitions in your design
  • Simulation of partial reconfiguration that allows you to observe the resulting change and the intermediate effect in a reconfiguration partition
  • Signal Tap logic analyzer debug with simultaneous acquisition of both the static region and partial reconfiguration regions