This article contains information about L3 cache of an Intel® Xeon® Scalable Processor and why the value is higher than L1 cache.
There's a difference of cache memory between Intel® Xeon® E5 Processors and Intel® Xeon® Scalable Processors.
Different cache hierarchy is expected. The cache hierarchy was changed in the architecture of the newer Intel® Xeon® Scalable processor families.
What are the cache hierarchy changes?
In prior architectures (such as the Intel® Xeon® E5 v4 Processor family):
- The mid-level cache (MLC or also known as L2) was 256 KB per core.
- The last level cache (also known as L3) was a shared inclusive cache with 2.5 MB per core.
In the architecture of the Intel® Xeon® Scalable Processor family, the cache hierarchy has changed to provide a larger MLC of 1 MB per core and a smaller shared non-inclusive 1.375 MB LLC per core. A larger MLC increases the hit rate into the MLC resulting in lower effective memory latency and also lowers demand on the mesh interconnect and LLC. The shift to a non-inclusive cache for the LLC allows for more effective utilization of the overall cache on the chip versus an inclusive cache.
For additional details, see the Cache Hierarchy Changes section of the Intel® Xeon® Processor Scalable Family Technical Overview.