Description
The High Performance Controller II (HPCII) used by the DDR2 UniPHY and ALTMEMPHY cores issues back to back read/write commands on every other controller clock cycle (afi_clk
).
If you have the burst length set to 4 for a half rate controller, then the controller will only use 50% of the maximum efficiency on the bus. This is an expected behavior of the half rate controller for burst length of 4 implementation.
Resolution
There are two workarounds:
- Use a full-rate HPCII controller when you set the burst length to 4.
- Use a half-rate HPCII controller when you set the burst length to 8.