The Encounter Conformal software may report this error while reading the revised netlist. This occurs because the Verilog Output File (.vo) netlist generated by the Quartus® II software contains an additional port in the instantiated black-box module that is not defined in the synthesis or the simulation module. The port is usually a control signal that controls both register and combinational logic inside the black-box hierarchy.
The workaround for this problem is to add the following command during the setup mode of the design. This command instructs Conformal to ignore the error that is caused by the additional port.
set rule handling HRC3.3 -ignore
For more information on formal verification using Conformal, refer to the Cadence Encounter Conformal Support (PDF) chapter in volume 3 of the Quartus II Handbook.