Article ID: 000074476 Content Type: Troubleshooting Last Reviewed: 07/11/2015

Cyclone V Hard IP for PCI Express IP Core VHDL Model Might Not Simulate Successfully with ModelSim-Altera Simulator

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    If you generate a VHDL simulation model for a Cyclone V Hard IP for PCI Express IP core Gen2 x4 endpoint variation, you cannot simulate your IP core successfully with the ModelSim-Altera simulator.

    Resolution

    This issue has no workaround. You must use a Verilog HDL simulation model for this IP core variation, or simulate with a different simulation tool.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs