You will observe the tx_coreclock obtained is half of the expected tx_coreclock frequency for odd serialization factors.
The work around RTL fix by generating another PLL output (clk2) for tx_coreclock.
1. Edit the following files after generation of Altera ®Soft LVDS IP
- <toplevel_name>_sim/<toplevel_name>.v
- <toplevel_name>/<toplevel_name>_002.v
2. Edit the PLL by adding clk2 parameters and following changes for the above mentioned files in the respective modules
- module <toplevel_name>_002 (<toplevel_name>/<toplevel_name>_002.v)
- module <toplevel_name> (<toplevel_name>_sim/<toplevel_name>.v)
step 1:-Add clk2 in 'defparam' section
lvds_tx_pll.clk2_divide_by = clk1_divide_by value
lvds_tx_pll.clk2_multiply_by = 2* clk1_multiply_by value
lvds_tx_pll.clk2_phase_shift = clk1_phase_shift value
step 2:- comment the tx_coreclock assignment and add the generated clock(clk2) from PLL to tx_coreclock as shown.
//tx_coreclock = slow_clock,
tx_coreclock = wire_lvds_tx_pll_clk[2],
This work around has been implemented in Intel Quartus® Prime Standard Edition software version 16.0 onwards.