Is there a known issue with simulating the Cyclone 10 LP PLL IP using Verilog?

Due to a problem in the Intel® Quartus® Prime Standard Edition software version 17.0, the PLL simulation model is not instantiated for Cyclone® 10 LP devices when performing simulation using Verilog. This issue does not apply when simulating the Cyclone 10 LP PLL IP using VHDL.

To fix this issue install patch below on top of Intel Quartus Prime Standard version 17.0 and follow the instruction to add extra steps in your simulation run script.

if ![file isdirectory verilog_libs] {
    file mkdir verilog_libs
}

vlib verilog_libs/altera_mf_ver
vmap altera_mf_ver ./verilog_libs/altera_mf_ver
vlog -vlog01compat -work altera_mf_ver {c:/intelfpga/17.0/quartus/eda/sim_lib/altera_mf.v}

quartus-17.0std-0.12std-windows.exe

quartus-17.0std-0.12std-linux.run

quartus-17.0std-0.12std-readme.txt

This problem is fixed beginning with the Intel Quartus Prime Standard Edition software version 18.0