Article ID: 000074712 Content Type: Troubleshooting Last Reviewed: 08/17/2022

Why does a design with a TX and RX Soft-CDR LVDS SERDES assigned to the same bank in an Intel® Arria® 10 device fail to fit?

Environment

  • Quartus® II Subscription Edition
  • LVDS SERDES Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a bug in the Quartus® II software, a design that has LVDS SERDES IP core configured in TX mode and RX Soft-CDR mode assigned to the same I/O bank in an Intel® Arria® 10 device will fail at the fitter stage.  This is because the phase-locked loop (PLL) instances within the two IP cores will not be correctly merged by the Quartus® II software. Therefore different PLLs will be required for the different LVDS SERDES IP cores. Each I/O bank has only one I/O PLL though.

    This problem only affects the RX Soft-CDR configuration.  RX Non-DPA or RX DPA-FIFO configurations are not affected.

    Note that the Triple Speed Ethernet IP core uses LVDS SERDES IP configured in RX Soft-CDR mode.

    Resolution

    Download the following patch for version 14.0 Intel Arria 10 FPGA Edition of the Quartus® II software:

    This problem is fixed starting with the Quartus® II software version 14.1.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 SX SoC FPGA
    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA