Article ID: 000075085 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Do multipliers simulate incorrectly when I target DSP Blocks in the Quartus II software version 2.1 SP2 and earlier?

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Description

Yes, in the Quartus® II software versions earlier than version 2.2, there is a known issue that affects simulation of multipliers when they are implemented in DSP blocks. 

The problem is fixed in beginning with the Quartus II software version 2.2.

The following configurations are affected in version 2.1 SP1 and earlier:

  • Mixed-sign multiplications of 19 bits and greater
  • Dynamic-sign multiplications of 19 bits and greater
  • Signed multiplications greater than 36 bits

 

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Stratix® FPGAs