Article ID: 000075146 Content Type: Product Information & Documentation Last Reviewed: 03/17/2023

How can the fractional PLL bandwidth parameter be set to "high" in the PLL reconfiguration calculator for Stratix® V, Arria® V, or Cyclone® V devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

In the phase-locked loop (PLL) reconfiguration calculator for Stratix® V, Arria® V, or Cyclone® V devices, the fractional PLL bandwidth setting is fixed to "low". It is not possible to modify the bandwidth setting in the calculator because the jitter specification in the datasheet only covers fractional PLLs with low bandwidth.

Resolution

If you need to reconfigure your fractional PLL bandwidth setting to "high", invoke the PLL Intel FPGA IP parameter editor, and enter the bandwidth settings along with the required counter settings. Generate a MIF file and look for the bit settings in this MIF file.

Related Products

This article applies to 14 products

Stratix® V GX FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Cyclone® V GX FPGA
Cyclone® V GT FPGA