Article ID: 000075169 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why are single write transactions proceeded by a burst to SDRAM from a master in the FPGA lost when using Excalibur™ XA10 devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

This is a known issue. Possible workarounds are listed below:

  1. Do a read immediately following the write burst.
  2. Insert idle cycles between the last beat of the burst and the single write. The number of cycles inserted should insure that CAS cycles are complete before the write is seen by the SDRAM controller interface.

Related Products

This article applies to 1 products

Excalibur™