Article ID: 000075336 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Is there a problem with the settings of the clock frequency in the ALTLVDS_RX and ALTLVDS_TX megafunctions in the Quartus II software versions 10.1 and 10.1SP1?

Environment

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Description

Yes, there is a problem with the setting of the input clock frequency in the ALTLVDS_RX and ALTLVDS_TX megafunctions in the Quartus® II software versions 10.1 and 10.1SP1

If the data rate is set to a fractional value then the derived input clock frequency only shows values as an integer.

The PLL summary report will also not show the correct input clock frequency.

A patch is available to fix this problem for the Quartus II software version 10.1. Download and install Patch 0.40 from the appropriate link below.

    Download the Quartus II software version 10.1 Patch 0.40 for Windows (.exe)

    Download the Quartus II software version 10.1 Patch 0.40 for Linux (.tar)

    Download the Readme for the Quartus II software version 10.1 Patch 0.40 (.txt)

    This problem is fixed in the Quartus II software versions 11.0 and newer.

    Related Products

    This article applies to 3 products

    Stratix® II GX FPGA
    Stratix® III FPGAs
    Stratix® II FPGAs