Article ID: 000075503 Content Type: Product Information & Documentation Last Reviewed: 04/03/2023

How should I place the QDR II/QDR II+ mem_cq and mem_cq_n pins in Arria® V GX/GT/ST/SX devices?

Environment

  • Quartus® II Subscription Edition
  • QDR II and QDR II+ SRAM Controller with UniPHY Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    From the device pinout file, there is only one pin location available for both mem_cq and mem_cq_n pins.

    Resolution

    For these Arria® V devices, complementary strobes are not supported so only one of the mem_cq or mem_cq_n pins will be used depending on the read latency setting.

    Related Products

    This article applies to 10 products

    Cyclone® V GX FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Cyclone® V SE SoC FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA