Article ID: 000075517 Content Type: Troubleshooting Last Reviewed: 04/05/2022

Why do the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Examples in Gen3 configurations fail setup timing on the xcvr_reconfig_clk ?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Examples in Gen3 configurations fail xcvr_reconfig_clk setup timing when the P-Tile Debug Toolkit is enabled.
    The timing violation does not affect the P-Tile Debug Toolkit results.

    Resolution

    A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 21.2.
    Download and install Patch 0.23 from the appropriate link below.

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 DX FPGA
    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series