Article ID: 000076355 Content Type: Troubleshooting Last Reviewed: 05/24/2017

Why might RapidIO I port_ok status signal not assert after link re-initialization?

Environment

  • Intel® Quartus® Prime Pro Edition
  • RapidIO (IDLE1 up to 5.0 Gbaud) Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    port_ok status in bit-0, Port 0 Error and Status CSR (0x158) may stay at LOW after link re-initialization occurs. Link re-initialization  is done either  by the triggering of bit-23 PORT_DIS in Port 0 Control CSR (0x15C), or when link partner is performing reset. This may cause  fatal error during normal operation,

    This issue happens due to the following reasons:

    • The RapidIO core may be out of reset prior to transceiver coming out of reset. This causes the RapidIO core to start operation while the transceiver is still in reset.
    • The word re-alignment process is limited to lane 0, and will trigger only once during link re-initialization.

    This issue affects the following RapidIO I variants:

    • Arria® V/Cyclone® V with x2 mode.
    • Arria V/Cyclone V at baud rate 5000 Mbaud.
    • Arria V with x4 mode at baud rate 3125 Mbaud.
    Resolution

    To ensure that the transceiver is out of reset and ready to start any operations before the RapidIO core, qualify the RapidIO core reset with the transceiver ready status signals in module <your_ip>_riophy_reset:

    //TX_SIDE

     

    always @(posedge tx_clk or negedge reset_n)

    begin

            if (!reset_n) begin

                tx_ready_s0 <= 1'b0;

                tx_ready_s1 <= 1'b0;

     

            end else begin

                tx_ready_s0 <= tx_ready;

                tx_ready_s1 <= tx_ready_s0;

     

            end

     

    end

     

    always @ (posedge tx_clk or negedge reset_n) begin

     if(!reset_n)begin

        txreset_n_p2 <= 1'b0;

        txreset_n_p1 <= 1'b0;

        txreset_n <= 1'b0;

      end else begin

        if (!gxbpll_locked_tx_clk_d2 || !tx_ready_s1) begin

          txreset_n_p2 <= 1'b0;

          txreset_n_p1 <= 1'b0;

          txreset_n <= 1'b0;

        end else begin

          txreset_n_p2 <= 1'b1;

          txreset_n_p1 <= txreset_n_p2;

          txreset_n <= txreset_n_p1;

        end

      end

    end

     

    //RX_SIDE

     

    always @(posedge rx_clk or negedge reset_n)

    begin

        if (!reset_n) begin

            rx_ready_s0 <= 1'b0;

            rx_ready_s1 <= 1'b0;

     

        end else begin

            rx_ready_s0 <= rx_ready;

            rx_ready_s1 <= rx_ready_s0;

     

        end

    end

     

    always @ (posedge rx_clk or negedge reset_n) begin

     if(!reset_n)begin

        rxreset_n_p2 <= 1'b0;

        rxreset_n_p1 <= 1'b0;

        rxreset_n <= 1'b0;

      end else begin

        if (!rx_ready_s1) begin

            rxreset_n_p2<=1'b0;

            rxreset_n_p1<=1'b0;

            rxreset_n<=1'b0;

     

        end else begin

            rxreset_n_p2 <= 1'b1;

            rxreset_n_p1 <= rxreset_n_p2;

            rxreset_n <= rxreset_n_p1;

     

        end

      end

    end

     

    To trigger word re-alignment process manually, perform the following steps through the Avalon-MM phy_mgmt transceiver interface:

    (1) Assert phy_mgmt_write=1'b1 to specify the write operation.

    (2) Write data phy_mgmt_writedata=32'b0 into address phy_mgmt_address=9'h80 to target for lane 0.

    (3) Write data phy_mgmt_writedata=32'b1 into address phy_mgmt_address=9'h85 to assert rx_enapatternalign which will trigger word alignment operation for lane 0.

    (4) Write data phy_mgmt_writedata=32'b0 into address phy_mgmt_address=9'h85 to deassert rx_enapatternalign.

    Repeat the steps above for all other lanes: lane 1 (0x80=32'b1), lane 2 (0x80=32'b2), and lane 3 (0x80=32'b3).

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs