Article ID: 000076518 Content Type: Error Messages Last Reviewed: 09/11/2019

Error(18090): External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column.

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
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    Description

    Due to a problem in the Intel® Quartus® Prime software version 19.2 or earlier, you may see the fitter error message when you aren't sharing the same clock and reset signals across multiple Intel Arria® 10 EMIF IP in the same I/O column. This message is incorrect, and you can follow the guidelines as described in the Intel Arria 10 EMIF IP User Guide. To place multiple interfaces in the same I/O column, you must ensure that the global reset signals (global_reset_n) for each individual interface all come from the same input pin or signal.

     

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs