Article ID: 000076614 Content Type: Error Messages Last Reviewed: 01/18/2023

Error(13149): EMIF/PHYLite systems sharing a PLL reference clock do not have identical reset inputs for following io_aux atoms

Environment

  • Intel® Quartus® Prime Pro Edition
  • PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When you implement an Intel® Arria® 10 External Memory Interfaces IP and an Intel Arria 10 PHYLite IP sharing the PLL reference clock and reset in the same I/O column, you may see this fitter error.

     

    Resolution

    To work around this problem, tie the Intel® Arria® 10 PHYLite IP reset port to "1".  

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs