Article ID: 000076646 Content Type: Product Information & Documentation Last Reviewed: 05/30/2017

How do I fix hold timing violations between the c2p_write_clk and the pll_write_clk for a Stratix V DDR3 design?

Environment

  • Quartus® II Subscription Edition
  • DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    For a Stratix® V DDR3 UniPHY-based design, you may see hold timing violations on data paths between the c2p_write_clk and the pll_write_clk clock domains.

    Resolution

    To resolve these hold timing violations, follow the steps below:

    1) In the IP-generated <IP_variation_name>if0_pll0.sv file, set

    parameter WRITE_CLK_PHASE = "938 ps"

    2) In the IP-generated <IP_variation_name>if0_p0_parameters.tcl file, set

    set ::GLOBAL_mem_if_ddr3_emif_example_design_example_if0_p0_pll_phase(PLL_WRITE_CLK) 270.0

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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