Article ID: 000076817 Content Type: Troubleshooting Last Reviewed: 11/12/2013

Stratix® II Device Handbook: Known Issues

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Description

Issue 367361, Volume 2, Chapter 2 "TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices", Version 4.5

Table 2-1 in the Stratix II Device Handbook and Table 8-1 in the Stratix II GX Device Handbook should show "16K x 36" as an available configuration for M-RAM blocks.

Issue 132933: Volume 2, Chapter 7. Configuring Stratix II and Stratix II GX Devices, Version 4.5

Table 7–22. Dedicated Configuration Pins on the Stratix II and Stratix II GX Device. The table incorrectly states "When using EPC2 devices, only external 10-kΩ pull-up resistors should be used." in the descriptions for nSTATUS and CONF_DONE. This is for EPC1, not for EPC2. The table should say "When using EPC1 devices, only external 10-kΩ pull-up resistors should be used." in descriptions for nSTATUS and CONF_DONE.

Issue 1001910, Volume 2, Chapter 5, "High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices", Version 2.2

DPAUasge Guidelinesshow each fast PLL can drive up to 25 contiguous rows in DPA mode in a single bank (not including the reference clock row). This restriction was intended to ensure minimum skew between any two channels. Starting in the Quartus® II software version 8.0, this restriction has been removed. To account for skew between any two channels (which can also result from board level skew), use receiver data realignment to ensure alignment across multiple channels.

Issue10003860,Volume 2, Chapter 5 "DC & Switching Characteristics", Version 4.5

Table 5-1 shows the absolute maximum DC voltage (Vi) is 4.6V. This should be 4.0V. During AC transitions, the voltage can exceed 4.0V for duty cycles as shown in Table 5-2.

Issue 10003254, Volume 2, Chapter 7 "Configuring Stratix II & Stratix II GX Devices", Version 4.5

The JTAG TCK pull-down resistor value is incorrectly specified as 10k-ohms in Figure 7-35. The correct external pull-down resistor value is 1k-ohm. This stronger resistor ensures that the TCK signal is biased at a logic low level.

Issue 10003059, Volume 2, Chapter 4 "Selectable I/O Standards in Stratix II and Stratix II GX Devices", Version 4.6

Table 4-2 should show 1.2V HSTL is supported in I/O banks 9-12. The only I/O banks that do not support 1.2V HSTL is I/O banks 1, 2, 3, 5, and 6.

Issue 10001024, Volume 2, Chapter 3 "External Memory Interfaces in Stratix II and Stratix II GX Devices", Version 4.4.

The Stratix® II & Stratix II GX DLL frequency range specifications for frequency mode 2 have been enhanced. The new specifications are listed below:

 

 

 

 

 

 

Stratix II & Stratix II GX DLL Frequency Range Specifications

Frequency Mode

Frequency Range (MHz)

0

100 – 175

1

150 – 230

2

200 – 350 (-3 speed grade)

200 – 310 (-4 & -5 speed grades)

3

240 – 400 (-3 speed grade)

240 – 350 (-4 & -5 speed grades)

 

 

Issue 10005939, Volume 2, Chapter 13 "Configuring Stratix II& Stratix II GX Devices", Version 4.4.

Page 13-103incorrectly states in the pin descriptionthat "When using remote system upgrade in AS mode, the RUnLU pin is available as a general-purpose I/O pin". When not using remote or local update configuration modes, this pin is available as a general-purpose use I/O pin.