Article ID: 000076871 Content Type: Troubleshooting Last Reviewed: 05/05/2021

Why is there an unconstrained clock reported in the On-Chip Flash Intel® FPGA IP on Intel® MAX® 10?

Environment

  • Intel® Quartus® Prime Standard Edition
  • On-Chip Flash Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    An unconstrained clock is reported as shown below when using the On-Chip Flash Intel® FPGA IP on Intel® MAX® 10 :

    altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg

     

    Resolution

    This reported unconstrained path can be ignored as this is not a clock.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs