Article ID: 000076908 Content Type: Troubleshooting Last Reviewed: 02/10/2023

Why can't the IOPLL bandwidth register be read using PLL Reconfig Intel® FPGA IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • IOPLL Reconfig Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may encounter a problem performing a read transaction of the bandwidth register using the PLL Reconfig Intel® FPGA IP core in Intel® Arria® 10 devices. This affects reading the Loop Filter Setting and Charge Pump Setting of the IOPLL.

    No known issues are performing read transactions on other registers.

    There are no known issues performing write transactions on any registers, so there are no limitations in performing PLL reconfiguration using the IP. 

     

     

      

    Resolution

    There is no workaround. Avoid performing read transactions on the bandwidth register. 

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs