Description
Due to a known problem in Intel® Quartus® Prime Pro software version 19.4 and earlier, the JESD204C Intel® FPGA IP has a Control Bits (CS) range of 0 - 31. However the supported range is 0 - 3.
Resolution
Select Control Bits (CS) within 0 - 3 range when using the JESD204C Intel® FPGA IP. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.