Article ID: 000077367 Content Type: Troubleshooting Last Reviewed: 01/23/2020

Why doesn't assertion of the pll_powerdown input signal reset the Intel® Arria® 10 device fPLL?

Environment

  • Intel® Quartus® Prime Standard Edition
  • Intel® Quartus® Prime Pro Edition
  • fPLL Intel® Arria® 10 Cyclone® 10 FPGA IP
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    Description

    By default, the Intel® Arria® 10 fPLL IP core's internal reset signal is controlled by the Avalon-MM register but not the pll_powerdown input signal. Therefore, asserting the pll_powerdown input signal will not reset the Intel® Arria® 10 fPLL.

    Resolution

    Add the following QSF assignment to change the reset control from the Avalon-MM register to the pll_powerdown input:        

    set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS=1"

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs