Why does TimeQuest report the incorrect frequency for coreclkout when using the ATX PLL with the PCIe IP core for Intel® Stratix® V devices?

This problem occurs when implementing a Gen 1 or Gen 2 PCIe® IP core using the ATX PLL in the Arria® V GZ or Stratix® V device family.  For ES devices, the reported coreclkout is 1/4 the correct frequency.  For production devices, the reported coreclkout is 1/2 the correct frequency.

This can be seen in TimeQuest using Report Clocks.  Both coreclkout and observablecoreclkdiv will have the same incorrectly reported frequency as stated above. 

To work around this issue:

1.  Compile the design to determine what frequency TimeQuest is reporting. 
2.  Add the following SDC to constrain the \'coreclkout\':

create_clock -period <half of the TimeQuest-reported period> [get_pins -compatibility_mode {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|observablecoreclkdiv}]

For example, if TimeQuest reports a 16ns clock period for a production device, the SDC is:
create_clock -period 8.000 [get_pins -compatibility_mode {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|observablecoreclkdiv}]

It is important to use the "-compatibility_mode" option to use wildcards within the SDC for get_pins.