Article ID: 000078241 Content Type: Error Messages Last Reviewed: 09/06/2018

Critical Warning (18234): ATX PLLs <hierarchy>:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst and <hierarchy>:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst are 0 ATX PLLs apart. For ATX PL

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Critical Warning (18234): ATX PLLs :xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst and :xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst are 0 ATX PLLs apart. For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 6 ATX PLLs apart.

 

You may encounter the above critical warning if your Intel® Arria® 10 design includes two or more ATX PLL instances running at the same VCO frequency (within 100 Mhz).

Resolution

To work around this problem, you can manually place the ATX PLL instances running at the same VCO frequency (within 100MHz) such that the minimum spacing specified in the critical warning message is fulfilled.

The following is an example QSF constraint.

set_location_assignment HSSIPMALCPLL_1DB -to ":xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst"

You can find the ATX PLL coordinates from the Intel® Quartus® Prime Software Chip Planner.

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs