Article ID: 000079921 Content Type: Troubleshooting Last Reviewed: 11/23/2011

Write Timing Violation at 550MHz for QDR II and QDR II SRAM Controller with UniPHY

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Designs targeting Stratix V devices at 550MHz may produce write timing violations.

    Resolution

    There is no workaround for this issue.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs