Article ID: 000080174 Content Type: Troubleshooting Last Reviewed: 03/27/2023

Why is ODT asserted for more than one rank in my DDR3 UniPHY controller?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    If you have a multi-rank DDR3 UniPHY controller generated in the Quartus® II software version 12.1SP1 or later, you may see the ODT signals for multiple ranks assert simultaneously.

    There is a problem with ODT when the Memory format in the Memory Parameters tab of the MegaWizard™ Plug-In Manager is set to Discrete Device.

     

     

    Resolution

    The workaround is to change the Memory Format in the Memory Parameters tab to UDIMM.

    This problem is fixed starting with the Quartus® II software version 15.0.

    Related Products

    This article applies to 7 products

    Stratix® III FPGAs
    Stratix® V GT FPGA
    Stratix® V GX FPGA
    Stratix® IV GT FPGA
    Stratix® IV GX FPGA
    Stratix® V E FPGA
    Stratix® V GS FPGA

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.