Article ID: 000080247 Content Type: Product Information & Documentation Last Reviewed: 08/03/2023

How precise are the output clock frequencies generated by the Altera_PLL megafunction?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Altera_PLL megafunction will display one of two messages regarding its ability to provide the desired output clock frequencies.  If the actual output clock frequency is within 0.5Hz of the requested output clock frequency, the message window will display the following:

"Info: fpll: Able to implement PLL with user settings"

If the actual output clock frequency is greater than 0.5Hz from the requested output clock frequency, the following message will be displayed:

“Warning: fpll: Able to implement PLL - Actual settings differ from Requested settings”

 

 

Resolution

To determine the actual output clock frequency for PLLs operating in integer mode, you can use the equations shown in Phase-Locked Loop Basics, PLL.

To determine the actual output clock frequency for PLLs operating in fractional mode, you can refer to the related solution below.

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