Article ID: 000080779 Content Type: Troubleshooting Last Reviewed: 06/06/2023

Why is the generated clock is not correct when there are multiple Intel® P-Tile Avalon® streaming for PCI Express instances?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.3, PCIe clocks might not be generated correctly when there are multiple Intel P-Tile Avalon® streaming for PCI Express instances with different configurations. This problem occurs in designs targeting Intel Agilex® devices (P-Tile). The IP-generated SDC file includes wildcards for matching the clock path, this results in only the first PCIe IP's SDC file being read correctly.

    Resolution

    To work around the problem, use the attached SDC file to replace the one generated in <IP instance>/intel_pcie_ptile_ast_310/synth/intel_ptile_pcie.sdc. 

    intel_ptile_pcie.sdc

    The problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 20.4.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series